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參數(shù)資料
| 型號(hào)： | CDB5529 |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 3/31頁(yè) |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR CS5529 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 303 |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±2.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 2.6mW @ 2.5V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5529 |
| 已供物品： | 板，線纜，磁盤 |
| 產(chǎn)品目錄頁(yè)面： | 755 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | CS5529-ASZR-ND - IC ADC 16BIT W/6BIT LATCH 20SSOP 598-1110-5-ND - IC ADC 16BIT W/6BIT LATCH 20SSOP |
| 其它名稱： | 598-1015 |
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CS5529
DS246F5
11
ages. The differential voltage between VREF+ and
VREF- sets the nominal full scale input span of the
converter. For a single-ended reference voltage,
such as the LT1019-2.5, the reference output is
connected to the VREF+ pin of the CS5529 and the
ground reference for the LT1019-2.5 is connected
to the VREF- pin.
Serial Port
The CS5529 includes a microcontroller with a
command register, a configuration register, a con-
version data register (read only), and a gain and off-
set register for calibration. All registers, except the
8-bit command register, are 24-bits in length. Fig-
ure 3 illustrates a block diagram of all the internal
register.
After a system initialization or reset, the serial port
is set to the command mode. The converter stays in
this mode until a valid 8-bit command is received
(the first 8-bits into the serial port). Once a valid 8-
bit command is received and interpreted by the
ADC’s command register, the serial port enters the
data mode. In data mode the next 24 serial clock
pulses shift data either into or out of the serial port
(72 serial clock pulses are needed if the setup reg-
ister command is issued). The Command Register
Descriptions section illustrates all valid com-
mands.
AIN
C = 20pF
f = 32.768 kHz
φ Coarse
1
φ Fine
1
V
≤ 25mV
i = fV
C
os
n
Figure 1. Input models for AIN+ and AIN- pins.
VREF
C = 10pF
f = 32.768 kHz
2
φ Fine
1
V
≤ 25mV
i = fV
C
os
n
φ Coarse
Figure 2. Input model for VREF+ and VREF- pins.
Latch Outputs
Low Power Mode
Output Word Rates
Unipolar/Bipolar
Reset System
etc.
Configuration Register (1 × 24)
Serial
Interface
CS
SDI
SDO
SCLK
Command Register (1 × 8)
Wr
it
e
O
n
ly
Re
a
d
O
n
ly
Conversion Data Register (1x24)
Gain Register (1 × 24)
Offset Register (1 × 24)
Figure 3. CS5529 Register Diagram.
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