參數(shù)資料
型號(hào): CDB5381
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 11/16頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR CS5381 192KHZ ADC
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 2
位數(shù): 24
采樣率(每秒): 192k
數(shù)據(jù)接口: 串行
輸入范圍: 6.1 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): 360mW @ 5V
工作溫度: -10°C ~ 70°C
已用 IC / 零件: CS5381
已供物品: 板,CD
產(chǎn)品目錄頁(yè)面: 755 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: CS5381-KZZR-ND - IC ADC AUD 120DB 192KHZ 24-TSSOP
CS5381-KSZR-ND - IC ADC AUD 120DB 192KHZ 24-SOIC
598-1092-5-ND - IC ADC AUD 120DB 192KHZ 24-TSSOP
598-1091-5-ND - IC ADC AUD 120DB 192KHZ 24-SOIC
其它名稱: 598-1008
4
DS563F2
CS5381
1. PIN DESCRIPTIONS
Pin Name
#
Pin Description
RST
1
Reset (Input) - The device enters a low power mode when low.
M/S
2
Master/Slave Mode (Input) - Selects operation as either clock master or slave.
LRCK
3
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
SCLK
4
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
MCLK
5
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VD
6
Digital Power (Input) - Positive power supply for the digital section.
GND
7,18
Ground (Input) - Ground reference. Must be connected to analog ground.
VL
8
Logic Power (Input) - Positive power for the digital input/output.
SDOUT
9
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
MDIV
10
MCLK Divider (Input) - Enables a master clock divide by two function.
HPF
11
High-Pass Filter Enable (Input) - Enables the Digital High-Pass Filter.
IS/LJ
12
Serial Audio Interface Format Select (Input) -Selects either the left-justified or IS format for the SAI.
M0
M1
13,14 Mode Selection (Input) - Determines the operational mode of the device.
OVFL
15
Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.
AINL+
AINL-
16, 17
Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
modulators via the AINL+/- pins.
VA
19
Analog Power (Input) - Positive power supply for the analog section.
AINR-
AINR+
20, 21
Differential Right Channel Analog Input (Input) -Signals are presented differentially to the delta-
sigma modulators via the AINR+/- pins.
VQ
22
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
REF_GND
23
Reference Ground (Input) - Ground reference for the internal sampling circuits.
FILT+
24
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
RST
124
FILT+
M/S
223
REFGND
LRCK
322
VQ
SCLK
421
AINR+
MCLK
520
AINR-
VD
619
VA
GND
718
GND
VL
817
AINL-
SDOUT
916
AINL+
MDIV
10
15
OVFL
HPF
11
14
M1
IS/LJ
12
13
M0
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