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參數(shù)資料
| 型號： | CDB5346 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 16/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR CS5346 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 3.15 Vpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 205mW @ 192kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5346 |
| 已供物品： | 板，纜線，CD |
| 產(chǎn)品目錄頁面： | 756 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | CS5346-CQZR-ND - IC ADC AUD 103DB 200KHZ 48-LQFP 598-1692-ND - IC ADC AUD 103DB 200KHZ 48LQFP |
| 其它名稱： | 598-1790 |
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DS861PP3
23
CS5346
5.6
PGA Auxiliary Analog Output
The CS5346 includes an auxiliary analog output through the PGAOUT pins. These pins can be configured
to output the analog input to the ADC as selected by the input MUX and gained or attenuated with the PGA,
or alternatively, they may be set to high impedance. See the “PGAOut Source Select (Bit 6)” on page 30 for
information on configuring the PGA auxiliary analog output.
The PGA auxiliary analog output can source very little current. Ascurrent from the PGAOUT pins increases,
distortion will increase. For this reason, a high-input impedance buffer must be used on the PGAOUT pins
to achieve full performance. An example buffer for PGAOUT is provided on the CDB5346 for reference. Re-
fer to the table in “DC Electrical Characteristics” on page 12 for acceptable loading conditions.
5.7
Control Port Description and Timing
The control port is used to access the registers, allowing the CS5346 to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port has two modes: SPI and IC, with the CS5346 acting as a slave device. SPI Mode is se-
lected if there is a high-to-low transition on the AD0/CS pin, after the RST pin has been brought high. IC
Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently
selecting the desired AD0 bit address state.
5.7.1
SPI Mode
In SPI Mode, CS is the chip-select signal; CCLK is the control port bit clock (input into the CS5346 from
the microcontroller); CDIN is the input data line from the microcontroller; CDOUT is the output data line
to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 14 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indi-
cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data that will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulled high or low with a 47 k resistor, if desired.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip ad-
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