參數(shù)資料
型號(hào)： CDB5346
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 14/38頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR CS5346
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 24
采樣率（每秒）： 192k
數(shù)據(jù)接口： 串行
輸入范圍： 3.15 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 205mW @ 192kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： CS5346
已供物品： 板，纜線，CD
產(chǎn)品目錄頁(yè)面： 756 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： CS5346-CQZR-ND - IC ADC AUD 103DB 200KHZ 48-LQFP
598-1692-ND - IC ADC AUD 103DB 200KHZ 48LQFP
其它名稱(chēng)： 598-1790
DS861PP3
21
CS5346
5.4
Analog Input Multiplexer, PGA, and Mic Gain
The CS5346 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier
(PGA). The input multiplexer can select one of six possible stereo analog input sources and route it to the
PGA. Analog inputs 4A and 4B are able to insert a +32 dB (+40x) gain stage before the input multiplexer,
allowing them to be used for microphone-level signals without the need for any external gain. The PGA
stage provides 12 dB (4x) adjustment in 0.5 dB steps. Figure 9 shows the architecture of the input multi-
plexer, PGA, and microphone gain stages.
The ““Analog Input Selection (Bits 2:0)” on page 32” outlines the bit settings necessary to control the input
- Address 08h” on page 31 outline the register settings necessary to control the PGA. By default, line-
level input 1 is selected, and the PGA is set to 0 dB.
5.5
Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject sig-
nals within the stopband of the filter. However, there is no rejection for input signals
which are
(n 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram
for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capac-
itors which have a lar ge voltage coefficient (such as ge neral-purpose ceramics) must be avoided since
these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
5.5.1
Analog Input Configuration for 1 VRMS Input Levels
The CS5346 PGA, excluding the input multiplexer, is shown in Figure 10 with nominal component values.
Interfacing to this circuit is a relatively simple matter and several options are available. The simplest option
is shown in Figure 11. However, it may be advantageous in some applications to provide a low-pass filter
prior to the PGA to prevent radio frequency interference within the amplifier. The circuit shown in Figure 12
MUX
+32 dB
AIN1A
AIN2A
AIN3A
AIN4A/MICIN1
AIN5A
AIN6A
PGA
MUX
+32 dB
AIN1B
AIN2B
AIN3B
AIN4B/MICIN2
AIN5B
AIN6B
Analog Input
Selection Bits
Channel A
PGA Gain Bits
Channel B
PGA Gain Bits
Out to ADC
Channel A
Out to ADC
Channel B
PGA
Figure 9. Analog Input Architecture
相關(guān)PDF資料
PDF描述
CDB5345 EVALUATION BOARD FOR CS5345
ASM06DSEN-S243 CONN EDGECARD 12POS .156 EYELET
ASM06DSEH-S243 CONN EDGECARD 12POS .156 EYELET
MLG1005S82NJ INDUCTOR MULTILAYER 82NH 0402
CDB5341 BOARD EVAL FOR CS5341 STEREO ADC
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