參數(shù)資料
型號(hào)： CDB4354
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 6/24頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD 5V DAC 2VRMS LINEDVR
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 192k
數(shù)據(jù)接口： I²S，串行
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： CS4354
產(chǎn)品目錄頁(yè)面： 757 (CN2011-ZH PDF)
其它名稱： 598-1809
CDB4354-ND
14
DS895F2
CS4354
4.4
Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4354 supports both external
and internal serial clock generation modes. Refer to Figure 6 for a diagram of the IS data format.
In order to support selectable de-emphasis without a dedicated pin, pin 5 (SCLK/DEM) functions both as
a serial clock input and a de-emphasis select. In typical applications where de-emphasis is not required,
the SCLK/DEM pin is the input for an external serial clock - this is known as the External Serial Clock
Mode. To enable de-emphasis selection, the Internal Serial Clock Mode has to be used. Sections 4.4.1
and 4.4.2 describe this feature in detail.
4.4.1
External Serial Clock Mode
The CS4354 will enter the External Serial Clock Mode when 16 low to high transitions are detected on the
SCLK/DEM pin during any phase of the LRCK period. When this mode is enabled, the Internal Serial
Clock Mode and de-emphasis filter are disabled (see Figure 9 for flow diagram).
In the External Serial Clock Mode, the CS4354 will support up to 24-bit IS data, with data valid on the
rising edge of SCLK.
4.4.2
Internal Serial Clock Mode
The CS4354 will switch to Internal Serial Clock Mode if no low to high transitions are detected on the
SCLK/DEM pin for 2 consecutive frames of LRCK (see Figure 9 for flow diagram). In the Internal Serial
Clock Mode, the serial clock is internally derived and synchronous with MCLK and LRCK. The
SCLK/LRCK frequency ratio is either 32, 48, or 64 depending on the speed mode and MCLK frequency.
Operation in this mode is identical to operation with an external serial clock synchronized with LRCK. This
mode allows access to the digital de-emphasis function. Refer to Table 5 for details (all frequencies listed
as multiples of LRCK frequency).
Table 5. Internal SCLK Frequencies
4.4.2.1
De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 7 shows the de-emphasis curve for Fs equal to
44.1 kHz. The frequency response of the de-emphasis curve scales with changes in the sample rate, Fs.
The de-emphasis error will increase for sample rates other than 44.1 kHz.
When the SCLK/DEM pin is connected to VL (internal SCLK mode), the 44.1 kHz de-emphasis filter is
activated. When the SCLK/DEM pin is connected to GND, the de-emphasis filter is disabled. For more
De-emphasis selection is disabled in the external SCLK mode.
Speed Mode
MCLK =
128x
192x
256x
384x
512x
768x
1024x
SSM
-
64x
48x
64x
DSM
-
48x
--
---
QSM
-
32x
-
LR C K
SC LK
Left C ha nnel
Rig ht C hannel
SDIN
+3 +2 +1
+5 +4
MSB
-1 -2 -3 -4 -5
+3 +2 +1
+5 +4
-1 -2 -3 -4
MSB
LSB
Figure 6. CS4354 Data Format (IS)
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