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參數(shù)資料
| 型號： | CD74ACT283M96 |
| 英文描述： | BINARY ADDER|ACT-CMOS|SOP|16PIN|PLASTIC |
| 中文描述： | 二進(jìn)制加法器|行為的CMOS |?？苵 16PIN |塑料 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 86K |
| 代理商： | CD74ACT283M96 |
CD54AC08, CD74AC08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS307B
–
JANUARY 2001
–
REVISED MAY 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
Continuous output current, I
O
(V
O
= 0 to V
CC
)
Continuous current through V
CC
or GND
Package thermal impedance,
θ
JA
(see Note 2): E package
–
0.5 V to 6 V
±
20 mA
±
50 mA
±
50mA
±
100 mA
80
°
C/W
86
°
C/W
–
65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under
“
absolute maximum ratings
”
may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under
“
recommended operating conditions
”
is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25
°
C
MIN
1.5
CD54AC08
CD74AC08
UNIT
MAX
5.5
MIN
1.5
MAX
5.5
MIN
1.5
MAX
5.5
VCC
Supply voltage
V
VCC = 1.5 V
VCC = 3 V
VCC = 5.5 V
VCC = 1.5 V
VCC = 3 V
VCC = 5.5 V
1.2
1.2
1.2
VIH
High-level input voltage
2.1
2.1
2.1
V
3.85
3.85
3.85
0.3
0.3
0.3
VIL
Low-level input voltage
0.9
0.9
0.9
V
1.65
1.65
1.65
VI
VO
IOH
IOL
Input voltage
0
VCC
VCC
–
24
0
VCC
VCC
–
24
0
VCC
VCC
–
24
V
Output voltage
0
0
0
V
High-level output current
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC = 1.5 V to 3 V
VCC = 3.6 V to 5.5 V
mA
Low-level output current
24
24
24
mA
t/
v
Input transition rise or fall rate
0
50
0
50
0
50
ns/V
0
20
0
20
0
20
TA
Operating free-air temperature
–
55
125
–
40
85
°
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
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