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參數(shù)資料
| 型號： | CD54HC4059 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter |
| 中文描述： | 高速CMOS邏輯CMOS可編程分頻氮計數(shù)器 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 209K |
| 代理商： | CD54HC4059 |
5
Prerequisite for Switching Specifications
PARAMETER
SYMBOL
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Pulse Width CP
t
W
2
90
-
-
115
-
-
135
-
-
ns
4.5
18
-
-
23
-
-
27
-
-
ns
6
15
-
-
20
-
-
23
-
-
ns
Setup Time
K
b
, K
c
to CP
t
SU
2
75
-
-
95
-
-
110
-
-
ns
4.5
15
-
-
19
-
-
22
-
-
ns
6
13
-
-
16
-
-
19
-
-
ns
CP Frequency
f
MAX
2
5
-
-
4
-
-
4
-
-
MHz
4.5
27
-
-
22
-
-
18
-
-
MHz
6
32
-
-
26
-
-
21
-
-
MHz
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Propagation Delay,
CP to Q
t
PLH
, t
PHL
C
L
= 50pF
2
-
-
200
-
250
-
300
ns
4.5
-
-
40
-
50
-
60
ns
6
-
-
34
-
43
-
51
ns
C
L
= 15pF
5
-
17
-
-
-
-
-
ns
Propagation Delay,
LE to Q
t
PLH
, t
PHL
C
L
= 50pF
2
-
-
175
-
220
-
265
ns
4.5
-
-
35
-
44
-
53
ns
6
-
-
30
-
37
-
45
ns
C
L
= 15pF
5
-
14
-
-
-
-
-
ns
Output Transition Time
t
THL
, t
TLH
C
L
= 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
CP Frequency
f
MAX
C
L
= 15pF
5
-
54
-
-
-
-
-
MHz
Input Capacitance
C
I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 5, 6)
C
PD
-
5
-
36
-
-
-
-
-
pF
NOTES:
5. C
PD
is used to determine the dynamic power consumption, per package.
6. P
D
= C
PD
V
CC2
f
i
+
Σ
C
L
V
CC2
f
o
where f
i
= input frequency, f
o
= output frequency, C
L
= output load capacitance, V
CC
= supply voltage.
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