參數(shù)資料
型號(hào)： CD54HC166W
廠(chǎng)商： Texas Instruments, Inc.
英文描述： High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register
中文描述： 高速CMOS邏輯8位Parallel-In/Serial-Out移位寄存器
文件頁(yè)數(shù)： 7/8頁(yè)
文件大?。?/td> 56K
代理商： CD54HC166W
7
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
Test Circuits and Waveforms
(Continued)
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns
t
f
= 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
t
r
= 6ns
t
f
= 6ns
90%
t
r
C
L
t
f
C
L
GND
V
CC
50%
GND
V
CC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
t
SU(H)
OUTPUT
SET, RESET
OR PRESET
V
CC
50%
90%
10%
50%
90%
t
REM
t
PLH
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
t
H(H)
t
r
C
L
t
f
C
L
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V
1.3V
1.3V
1.3V
90%
1.3V
90%
110%
t
REM
t
PLH
t
SU(H)
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
1.3V
t
H(H)
CD74HC166, CD74HCT166
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