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參數(shù)資料
| 型號： | CD54HC166W |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register |
| 中文描述： | 高速CMOS邏輯8位Parallel-In/Serial-Out移位寄存器 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 56K |
| 代理商： | CD54HC166W |
5
MR Pulse Width
(Figure 1)
t
w
2
100
-
125
-
150
-
ns
4.5
20
-
25
-
30
-
ns
6
17
-
21
-
26
-
ns
Clock Pulse Width
(Figure 1)
t
W
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
Set-up Time
Data and CE to Clock
(Figure 5)
t
SU
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
Hold Time
Data to Clock
(Figure 5)
t
H
2
1
-
1
-
1
-
ns
4.5
1
-
1
-
1
-
ns
6
1
-
1
-
1
-
ns
Removal Time
MR to Clock
(Figure 5)
t
REM
2
0
-
0
-
0
-
ns
4.5
0
-
0
-
0
-
ns
6
0
-
0
-
0
-
ns
Set-up Time
PE to CP
(Figure 5)
t
SU
2
145
-
180
-
220
-
ns
4.5
29
-
36
-
44
-
ns
6
25
-
31
-
38
-
ns
Hold Time
PE to CP or CE
(Figure 5)
t
H
2
0
-
0
-
0
-
ns
4.5
0
-
0
-
0
-
ns
6
0
-
0
-
0
-
ns
HCT TYPES
Clock Frequency (Figure 2)
f
MAX
4.5
25
-
20
-
16
-
MHz
MR Pulse Width (Figure 2)
t
w
4.5
35
-
44
-
53
-
ns
Clock Pulse Width (Figure 2)
t
w
4.5
20
-
25
-
30
-
ns
Set-up Time Data and CE to
Clock (Figure 6)
t
SU
4.5
16
-
20
-
24
-
ns
Hold Time Data to Clock
(Figure 6)
t
H
4.5
0
-
0
-
0
-
ns
Removal Time MR to Clock
(Figure 6)
t
REM
4.5
0
-
0
-
0
-
ns
Set-up Time PE to CP (Figure 6)
t
SU
4.5
30
-
38
-
45
-
ns
Hold Time PE to CP or CE
(Figure 6)
t
H
4.5
0
-
0
-
0
-
ns
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
TYP
MAX
MAX
MAX
HC TYPES
Propagation Delay,
Clock to Output (Figure 3)
t
PLH
, t
PHL
C
L
= 50pF
2
-
160
200
240
ns
4.5
-
32
40
48
ns
C
L
= 15pF
CL = 50pF
5
13
-
-
-
ns
6
-
27
34
41
ns
Prerequisite For Switching Specifications
(Continued)
PARAMETER
SYMBOL
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
CD74HC166, CD74HCT166
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