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參數(shù)資料
| 型號(hào)： | CD4723BM |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual 4-Bit, 8-Bit Addressable Latch |
| 中文描述： | 雙4位，8位可尋址鎖存器 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 146K |
| 代理商： | CD4723BM |
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, R
L
e
200k, Input t
r
e
t
f
e
20 ns, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHL, tPLH
Propagation Delay
Data to Output
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
200
75
50
400
150
100
ns
ns
ns
t
PLH
, t
PHL
Propagation Delay
Enable to Output
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
200
80
60
400
160
120
ns
ns
ns
t
PHL
Propagation Delay
Clear to Output
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
175
80
65
350
160
130
ns
ns
ns
t
PLH
, t
PHL
Propagation Delay
Address to Output
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
225
100
75
450
200
150
ns
ns
ns
t
THL
, t
TLH
Transition Time
(Any Output)
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
100
50
40
200
100
80
ns
ns
ns
T
WH
, T
WL
Minimum Data
Pulse Width
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
100
50
40
200
100
80
ns
ns
ns
t
WH
, t
WL
Minimum Address
Pulse Width
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
200
100
65
400
200
125
ns
ns
ns
t
WH
Minimum Clear
Pulse Width
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
75
40
25
150
75
50
ns
ns
ns
t
SU
Minimum Setup Time
Data to E
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
40
20
15
80
40
30
ns
ns
ns
t
H
Minimum Hold Time
Data to E
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
60
30
25
120
60
50
ns
ns
ns
t
SU
Minimum Setup Time
Address to E
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
b
15
0
0
50
30
20
ns
ns
ns
t
H
Minimum Hold Time
Address to E
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
b
50
b
20
b
15
15
10
5
ns
ns
ns
C
PD
Power Dissipation
Capacitance
Per Package
(Note 4)
100
pF
C
IN
Input Capacitance
Any Input
5.0
7.5
pF
*
AC Parameters are guaranteed by DC correlated testing.
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device
operation.
Note 2:
V
SS
e
0V unless otherwise specified.
Note 3:
I
OL
and I
OH
are tested one output at a time.
Note 4:
Dynamic power dissipation (P
D
) is given by: P
D
e
(C
PD
a
C
L
) V
CC2
f
a
P
Q
; where C
L
e
load capacitance; f
e
frequency of operation; for further details,
see Application Note AN-90, ‘‘54C/74C Family Characteristics’’.
4
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