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參數(shù)資料
| 型號： | CD4724BCJ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 4-Bit, 8-Bit Addressable Latch |
| 中文描述： | 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 146K |
| 代理商： | CD4724BCJ |
TL/F/6003
C
C
February 1988
CD4723BM/CD4723BC Dual 4-Bit Addressable Latch
CD4724BM/CD4724BC 8-Bit Addressable Latch
General Description
The CD4723B is a dual 4-bit addressable latch with com-
mon control inputs, including two address inputs (A0, A1),
an active low enable input (E), and an active high clear input
(CL). Each latch has a data input (D) and four outputs (Q0–
Q3). The CD4724B is an 8-bit addressable latch with three
address inputs (A0–A2), an active low enable input (E), ac-
tive high clear input (CL), a data input (D) and eight outputs
(Q0–Q7).
Data is entered into a particular bit in the latch when that is
addressed by the address inputs and the enable (E) is low.
Data entry is inhibited when enable (E) is high.
When clear (CL) and enable (E) are high, all outputs are low.
When clear (CL) is high and enable (E) is low, the channel
demultiplexing occurs. The bit that is addressed has an ac-
tive output which follows the data input while all unad-
dressed bits are held low. When operating in the address-
able latch mode (E
e
CL
e
low), changing more than one
bit of the address could impose a transient wrong address.
Therefore, this should only be done while in the memory
mode (E
e
high, CL
e
low).
Features
Y
Wide supply voltage range
3.0V to 15V
0.45 V
DD
(typ.)
Y
High noise immunity
Y
Low power TTL
compatibility
fan out of 2 driving 74L
or 1 driving 74LS
Y
Serial to parallel capability
Y
Storage register capability
Y
Random (addressable) data entry
Y
Active high demultiplexing capability
Y
Common active high clear
Connection Diagrams
CD4723B
Dual-In-Line Package
TL/F/6003–1
Top View
CD4724B
Dual-In-Line Package
TL/F/6003–2
Top View
Order Number CD4723B or
CD4724B
Truth Table
Mode Selection
E
CL
Addressed
Latch
Unaddressed
Latch
Mode
L
H
L
H
L
L
H
H
Follows Data
Hold Previous Data
Follows Data
Reset to ‘0’’
Holds Previous Data
Holds Previous Data
Reset to ‘‘0’’
Reset to ‘‘0’’
Addressable Latch
Memory
Demultiplexer
Clear
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
相關PDF資料 |
PDF描述 |
|---|---|
| CD4724BCN | Dual 4-Bit, 8-Bit Addressable Latch |
| CD4724BM | Dual 4-Bit, 8-Bit Addressable Latch |
| CD4724BMJ | Dual 4-Bit, 8-Bit Addressable Latch |
| CD4724BMN | Dual 4-Bit, 8-Bit Addressable Latch |
| CD4724BCMX | Addressable D-Type Latch |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CD4724BCJ/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Addressable D-Type Latch |
| CD4724BCM | 功能描述:閉鎖 Dl 8-Bit Address Lat RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4724BCM_Q | 功能描述:閉鎖 Dl 8-Bit Address Lat RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4724BCMX | 功能描述:閉鎖 Dl 8-Bit Address Lat RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4724BCN | 功能描述:閉鎖 Dl 8-Bit Address Lat RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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