參數(shù)資料
型號(hào)： CD4094BMS
廠商： Intersil Corporation
英文描述： CMOS 8-Stage Shift-and-Store Bus Register(CMOS 8極移位與存儲(chǔ)總線寄存器)
中文描述： 的CMOS 8級(jí)移位和存儲(chǔ)總線寄存器（的CMOS 8極移位與存儲(chǔ)總線寄存器）
文件頁數(shù)： 2/11頁
文件大?。?/td> 87K
代理商： CD4094BMS
7-1084
Specifications CD4094BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±
10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
±
1/32 Inch (1.59mm
±
0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . .
Flatpack Package . . . . . . . . . . . . . . . .
Maximum Package Power Dissipation (PD) at +125
o
C
For TA = -55
o
C to +100
o
C (Package Type D, F, K). . . . . . 500mW
For TA = +100
o
C to +125
o
C (Package Type D, F, K) . . . . .Derate
θ
ja
θ
jc
80
o
C/W
70
o
C/W
20
o
C/W
20
o
C/W
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
(NOTE 1)
VDD = 20V, VIN = VDD or GND
GROUP A
SUBGROUPS
1
2
3
1
2
3
1
2
3
1, 2, 3
1, 2, 3
1
1
1
1
1
1
1
1
1
7
7
8A
8B
1, 2, 3
TEMPERATURE
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C 14.95
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
LIMITS
MIN
-
-
-
-100
-1000
-100
-
-
-
-
UNITS
μ
A
μ
A
μ
A
nA
nA
nA
nA
nA
nA
mV
V
mA
mA
mA
mA
mA
mA
mA
V
V
V
MAX
10
1000
10
-
-
-
100
1000
100
50
-
-
-
-
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
VOL <
VDD/2
VDD = 18V, VIN = VDD or GND
VIN = VDD or GND
Input Leakage Current
IIL
VDD = 20
VDD = 18V
VDD = 20
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 18V
Output Voltage
Output Voltage
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
VOL15
VOH15
IOL5
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VNTH
VPTH
F
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10
μ
A
VSS = 0V, IDD = 10
μ
A
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
0.53
1.4
3.5
-
-
-
-
-2.8
0.7
VOH >
VDD/2
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Tri-State Output
Leakage
VIL
-
1.5
V
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
3.5
-
V
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VIN = VDD or GND
VOUT = 0V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
4
V
VIH
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
11
-
V
IOZL
VDD = 20V
1
2
3
1
2
3
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
-0.4
-12
-0.4
-
-
-
-
-
-
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
VDD = 18V
VDD = 20V
Tri-State Output
Leakage
IOZH
VIN = VDD or GND
VOUT = VDD
0.4
12
0.4
VDD = 18V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
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