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參數(shù)資料
| 型號： | CD4043BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Quad 3 State R/S Latches(CMOS四 R/S鎖存器（三態(tài)）) |
| 中文描述： | 3國的CMOS四路的R / S鎖存器的CMOS（四的R / S鎖存器（三態(tài)）） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 110K |
| 代理商： | CD4043BMS |
7-876
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4043BMS
CD4044BMS
CMOS Quad 3 State R/S Latches
Pinout
CD4043BMS
TOP VIEW
CD4044BMS
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q4
Q1
R1
S1
ENABLE
S2
VSS
R2
VDD
S4
NC
S3
R3
Q3
Q2
R4
NC = NO CONNECTION
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q4
NC
S1
R1
ENABLE
R2
VSS
S2
VDD
R4
Q1
R3
S3
Q3
Q2
S4
NC = NO CONNECTION
Features
High Voltage Types (20V Rating)
Quad NOR R/S Latch- CD4043BMS
Quad NAND R/S Latch - CD4044BMS
3 State Outputs with Common Output ENABLE
Separate SET and RESET Inputs for Each Latch
NOR and NAND Configuration
5V, 10V and 15V Parametric Ratings
Standardized Symmetrical Output Characteristics
100% Tested for Quiescent Current at 20V
Maximum Input Current of 1
μ
a at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25
o
C
Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of ‘B’
Series CMOS Devices”
Applications
Holding Register in Multi-Register System
Four Bits of Independent Storage with Output ENABLE
Strobed Register
General Digital Logic
CD4043BMS for Positive Logic Systems
CD4044BMS for Negative Logic Systems
Description
CD4043BMS types are quad cross-coupled 3-state CMOS NOR
latches and the CD4044BMS types are quad cross-coupled 3-
state CMOS NAND latches. Each latch has a separate Q output
and individual SET and RESET inputs. The Q outputs are con-
trolled by a common ENABLE input. A logic “1” or high on the
ENABLE input connects the latch states to the Q outputs. A logic
“0” or low on the ENABLE input disconnects the latch states from
the Q outputs, results in an open circuit feature allows common
busing of the outputs.
The CD4043BMS and CD4044BMS are supplied in these 16-
lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4043B Only
*H4T
*H1C
*H3X
CD4044B Only
H4T
HIE
H6W
File Number
3311
December 1992
相關PDF資料 |
PDF描述 |
|---|---|
| CD4044BC | Quad 3-STATE NAND R/S Latches(四3態(tài)輸入與非邏輯R/S緩沖器) |
| CD4044BPW | Single 100Mbps Digital Isolator with Enable 8-SOIC -40 to 125 |
| CD4044BDWR | Single 100Mbps Digital Isolator 8-SOIC -40 to 125 |
| CD4043BPW | CMOS QUAD 3-STATE R/S LATCHES |
| CD4044 | CMOS QUAD 3-STATE R/S LATCHES |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CD4043BNS | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| CD4043BNSR | 功能描述:閉鎖 Tri-St. Quad NOR R/S RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4043BNSRE4 | 功能描述:閉鎖 Tri-St. Quad NOR R/S RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4043BNSRG4 | 功能描述:閉鎖 CMOS Quad NOR R/S RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4043BPW | 功能描述:閉鎖 CMOS Quad NOR R/S RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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