參數(shù)資料
型號： CD40192BMS
廠商： Intersil Corporation
元件分類： 通用總線功能
英文描述： CMOS Presettable Up/Down Counters (Dual Clock With Reset)(CMOS可預置加/減計數(shù)器（帶復位的雙時鐘）)
中文描述： 的CMOS可預置上/下計數(shù)器（雙時鐘復位）的CMOS（可預置加/減計數(shù)器（帶復位的雙時鐘））
文件頁數(shù)： 4/12頁
文件大?。?/td> 149K
代理商： CD40192BMS
7-1422
Specifications CD40192BMS, CD40193BMS
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
+125
o
C
-55
o
C
+125
o
C
-55
o
C
+125
o
C
-55
o
C
+125
o
C
-55
o
C
-
-0.36
mA
-
-0.64
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
-
-1.15
mA
-
-2.0
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
-
-0.9
mA
-
-1.6
mA
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
-
-2.4
mA
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
7
-
V
Propagation Delay
Clock Up or Down to Q
TPHL1
TPLH1
VDD = 10V
1, 2, 3
-
240
ns
VDD = 15V
1, 2, 3
-
180
ns
Propagation Delay
Reset to Q
TPHL2
VDD = 10V
1, 2, 3
-
240
ns
VDD = 15V
1, 2, 3
-
180
ns
Propagation Delay
PE to Q
TPHL3
TPLH3
VDD = 10V
1, 2, 3
-
200
ns
VDD = 15V
1, 2, 3
-
140
ns
Propagation Delay
Clock Up to Carry, Clock
Down to Borrow
TPHL4
TPLH4
VDD = 10V
1, 2, 3
-
160
ns
VDD = 15V
1, 2, 3
-
120
ns
Propagation Delay
PE to Borrow or Carry
TPHL5
TPLH5
VDD = 10V
1, 2, 3
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
-
300
ns
VDD = 15V
1, 2, 3
-
220
ns
Propagation Delay
Reset to Borrow or Carry
TPHL6
TPLH6
VDD = 10V
1, 2, 3
-
300
ns
VDD = 15V
1, 2, 3
-
220
ns
Transition Time
TTHL1
TTLH1
VDD = 10V
1, 2, 3
-
100
ns
VDD = 15V
1, 2, 3
-
80
ns
Maximum Clock Rise and
Fall Time
TRCL
TFCL
VDD = 5V
1, 2, 3, 4
-
15
μ
s
VDD = 10V
1, 2, 3, 4
-
15
μ
s
VDD = 15V
1, 2, 3, 4
-
5
μ
s
Minimum Removal Time
Reset or PE
TREM
VDD = 5V
1, 2, 3, 5
-
80
ns
VDD = 10V
1, 2, 3, 5
-
40
ns
VDD = 15V
1, 2, 3, 5
-
30
ns
Minimum Pulse Width
Reset
TW
VDD = 5V
1, 2, 3
-
480
ns
VDD = 10V
1, 2, 3
-
300
ns
VDD = 15V
1, 2, 3
-
260
ns
Minimum Pulse Width PE
TW
VDD = 5V
1, 2, 3
-
240
ns
VDD = 10V
1, 2, 3
-
170
ns
VDD = 15V
1, 2, 3
-
140
ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
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CD40192 CMOS Presettable Up/Down Counters (Dual Clock With Reset)
相關代理商/技術參數(shù)
參數(shù)描述
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