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參數(shù)資料
| 型號： | CD4016 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Quad Bilateral Switch |
| 中文描述： | 四雙邊開關(guān) |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 155K |
| 代理商： | CD4016 |
DC Electrical Characteristics
CD4016BC (Note 2) (Continued)
Symbol
Parameter
Conditions
b
40
§
C
25
§
C
85
§
C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device Current
V
DD
e
5V, V
IN
e
V
DD
or V
SS
V
DD
e
10V, V
IN
e
V
DD
or V
SS
V
DD
e
15V, V
IN
e
V
DD
or V
SS
1.0
2.0
4.0
0.01
0.01
0.01
1.0
2.0
4.0
7.5
15
30
m
A
m
A
m
A
Signal Inputs and Outputs
R
ON
‘‘ON’’ Resistance
R
L
e
10 k
X
toV
DD
b
V
SS
V
C
e
V
DD
, V
IS
e
V
SS
or V
DD
V
DD
e
10V
V
DD
e
15V
R
L
e
10 k
X
toV
DD
b
V
SS
V
C
e
V
DD
V
DD
e
10V, V
IS
e
4.75 to 5.25V
V
DD
e
15V, V
IS
e
7.25 to 7.75V
R
L
e
10 k
X
toV
DD
b
V
SS
V
C
e
V
DD
, V
IS
e
V
SS
to V
DD
V
DD
e
10V
V
DD
e
15V
V
C
e
0, V
DD
e
15V
V
IS
e
0V or 15V,
V
OS
e
15V or 0V
2
610
370
275
200
660
400
840
520
X
X
2
1900
790
850
400
2000
850
2380
1080
X
X
D
R
ON
D
‘‘ON’’ Resistance
Between any 2 of
4 Switches
2
15
10
X
X
(In Same Package)
I
IS
Input or Output Leakage
Switch ‘‘OFF’’
g
50
g
0.1
g
50
g
200
nA
Control Inputs
V
ILC
Low Level Input Voltage
V
IS
e
V
SS
and V
DD
V
OS
e
V
DD
and V
SS
I
IS
e
g
10
m
A
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
CC
b
V
SS
e
15V
V
DD
t
V
IS
t
V
SS
V
DD
t
V
C
t
V
SS
0.9
0.9
0.9
0.7
0.7
0.7
0.4
0.4
0.4
V
V
V
V
IHC
High Level Input Voltage
3.5
7.0
11.0
3.5
7.0
11.0
3.5
7.0
11.0
V
V
V
(see Note 6 and
Figure 8)
I
IN
Input Current
g
0.3
g
10
b
5
g
0.3
g
1.0
m
A
AC Electrical Characteristics
*
T
A
e
25
§
C, t
r
e
t
f
e
20 ns and V
SS
e
0V unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHL
, t
PLH
Propagation Delay Time
Signal Input to Signal Output
V
C
e
V
DD
, C
L
e
50 pF, (Figure 1)
R
L
e
200k
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
R
L
e
1.0 k
X
, C
L
e
50 pF, (Figures 2
and3)
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
R
L
e
1.0 k
X
, C
L
e
50 pF, (Figures 2
and3)
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
C
e
V
DD
e
5V, V
SS
eb
5
R
L
e
10 k
X
, V
IS
e
5 V
P-P
, f
e
1 kHz,
(Figure 4)
58
27
20
100
50
40
ns
ns
ns
t
PZH
, t
PZL
Propagation Delay Time
Control Input to Signal
Output High Impedance to
Logical Level
20
18
17
50
40
35
ns
ns
ns
t
PHZ
, t
PLZ
Propagation Delay Time
Control Input to Signal
Output Logical Level to
High Impedance
15
11
10
0.4
40
25
22
ns
ns
ns
%
Sine Wave Distortion
3
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