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參數(shù)資料
| 型號(hào)： | CD4015 |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output |
| 中文描述： | CMOS雙4級(jí)靜態(tài)移位寄存器在串行輸入/并行輸出 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 130K |
| 代理商： | CD4015 |
7-93
Specifications CD4015BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
O
C
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD
±
1.0
μ
A
Output Current (Sink)
IOL5
±
20% x Pre-Test Reading
Output Current (Source)
IOH5A
±
20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
READ AND RECORD
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
MIL-STD-883
METHOD
TEST
READ AND RECORD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
OPEN
GROUND
VDD
9V
±
-0.5V
OSCILLATOR
50kHz
25kHz
Static Burn-In 1
Note 1
2 - 5, 10 - 13
1, 6 - 9, 14, 15
16
Static Burn-In 2
Note 1
2 - 5, 10 - 13
8
1, 6, 7, 9, 14 - 16
Dynamic Burn-
In Note 1
-
6, 8, 14
16
2 - 5, 10 - 13
1, 9
7, 15
Irradiation
Note 2
2 - 5, 10 - 13
8
1, 6, 7, 9, 14 - 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K
±
5%, VDD = 18V
±
0.5V
2. Each pin except VDD and GND will have a series resistor of 47K
±
5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V
±
0.5V
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