參數(shù)資料
型號: CD40109BMS
廠商: Intersil Corporation
英文描述: CMOS Quad Low-to-High Voltage Level Shifter
中文描述: 的CMOS四路低到高電壓電平轉換器
文件頁數(shù): 6/9頁
文件大小: 76K
代理商: CD40109BMS
7-41
Specifications CD40109BMS
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
Group B
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9, Deltas
1, 7, 9
1, 7, 9, Deltas
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
1, 2, 3, 8A, 8B, 9
IDD, IOL5, IOH5A
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Group D
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
Subgroups 1, 2 3
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
MIL-STD-883
METHOD
5005
TEST
READ AND RECORD
PRE-IRRAD
1, 9
PRE-IRRAD
1, 7, 9
POST-IRRAD
Table 4
POST-IRRAD
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
OPEN
4, 5, 11-13
4, 5, 11-13
GROUND
2, 3, 6-10, 14, 15
8
VDD
1, 16
16
9V
±
-0.5V
OSCILLATOR
50kHz
25kHz
Static Burn-In 1 (Note 1)
Static Burn-In 2 (Note 1)
1-3, 4, 7, 9, 10,
14, 15
1, 4, 5, 11, 13
Dynamic Burn-In (Note 4)
12
8
16
3, 6, 10, 14
(Note 3)
2, 7, 9, 15
(Note 3)
Irradiation (Note 2)
4, 5, 11-13
8
1-3, 6, 7, 9, 10,
14-16
NOTES:
1. Each pin except Pin 1, VDD and GND will have a series resistor of 10K
±
5%, VDD = 18V
±
0.5V
2. Each pin except Pin 1, VDD and GND will have a series resistor of 47K
±
5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V
±
0.5V
3. Pin voltage is VDD/2
4. Each pin except Pin 1, VDD and GND will have a series resistor of 4.75K
±
5%, VDD = 18V
±
0.5V.
Logic Diagram
VCC
FIGURE 1. 1 OF 4 UNITS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
READ AND RECORD
LEVEL
SHIFTER
LEVEL
SHIFTER
A
ENABLE A
2 (7, 9, 15)
VDD
*
3 (6, 10, 14)
*
VSS
VDD
E
4 (5, 11, 13)
VCC = 1
VDD = 16
VSS = 8
VDD
VSS
*
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
TRUTH TABLE
INPUTS
OUTPUTS
A, B, C, D
ENABLE
A, B, C, D
E, F, G, H
0
1
0
1
1
1
X
0
Z
Logic 0 = Low(VSS)
X = Don’t care
Z = High impedance
Logic 1 = VCC at Inputs and VDD at Outputs
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