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參數(shù)資料
| 型號： | CD22354AE |
| 廠商： | INTERSIL CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | CMOS Single-Chip, Full-Feature PCM CODEC |
| 中文描述： | MU-LAW, PCM CODEC, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 55K |
| 代理商： | CD22354AE |
4-171
CD22354A, CD22357A
Hold Time from 3rd Period of Bit
Clock Low to Frame Sync
(FS
X
or FS
R
)
t
HBFI
Long Frame Sync Pulse
(from 3 to 8-Bit Clock Periods Long)
100
-
-
ns
Minimum Width of the Frame
Sync Pulse (Low Level)
t
WFL
64K Bit/s Operating Mode
160
-
-
ns
NOTE:
1. For short frame sync timing, FS
X
and FS
R
must go high while their respective bit clocks are high.
Pin Descriptions
PIN NO.
SYMBOL
DESCRIPTION
1
V-
Negative power supply, V- = -5V
±
5%.
2
GND
Analog and digital ground. All signals referenced to this pin.
3
VF
O
Analog output of RECEIVE FILTER.
4
V+
Positive power supply, V+ = 5V
±
5%.
5
FS
R
Receive Frame Sync Pulse which enables BCLK
R
to shift PCM data into D
R
. FS
R
is an 8kHz PULSE
TRAIN.
6
D
R
Receive Data Input. PCM data is shifted into D
R
following the FS
R
leading edge.
7
BCLK
R
/CLK-
SEL
The Receive Bit Clock, which shifts data into D
R
after the frame sync leading edge, may vary from 64kHz
to 2.048MHz. Alternatively, the leading edge may be a logic input which selects either 1.536MHz/
1.544MHz or 2.048MHz for Master Clock in synchronous mode and BCLK
X
is used for both transmit and
receive directions.
8
MCLK
R
/PDN
Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLK
X
,
but best performance is realized from synchronous operation. When this pin is continuously connected
low, MCLK
X
is selected for all internal timing. When this pin is continuously connected high, the device is
powered down.
9
MCLK
X
Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLK
R
,
but best performance is realized from synchronous operation.
10
BCLK
X
The Bit Clock which shifts out the PCM Data on D
X
. May vary from 64kHz to 2.048MHz, but must be syn-
chronous with MCLK
X.
11
D
X
The THREE-STATE PCM Data Output which is enabled by FS
X
.
12
FS
X
Transmit Frame Sync Pulse input which enables BCLK
X
to shift out the data on D
X
. FS
X
is an 8kHz
PULSE TRAIN.
13
TS
X
Open drain output which pulses low during the encoder time slot.
14
GS
X
Transmit gain adjust.
15
VF
X
I-
Inverting input of the transmit input amplifier.
16
VF
X
I+
Non-inverting input of the transmit input amplifier.
Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
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PDF描述 |
|---|---|
| CD22357A | CMOS Single-Chip, Full-Feature PCM CODEC |
| CD22357AE | CMOS Single-Chip, Full-Feature PCM CODEC |
| CD22402 | Sync Generator for TV Applications and Video Processing Systems |
| CD22402D | R8C Series, 23 Group, WDTO 48P6Q-A |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD22354AE WAF | 制造商:Harris Corporation 功能描述: |
| CD22354E | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD22357A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Single-Chip, Full-Feature PCM CODEC |
| CD22357AE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| CD22357AE WAF | 制造商:Harris Corporation 功能描述: |
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