- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379804 > CD22354AE (INTERSIL CORP) CMOS Single-Chip, Full-Feature PCM CODEC PDF資料下載
參數(shù)資料
| 型號： | CD22354AE |
| 廠商： | INTERSIL CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | CMOS Single-Chip, Full-Feature PCM CODEC |
| 中文描述： | MU-LAW, PCM CODEC, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 55K |
| 代理商： | CD22354AE |
4-170
CD22354A, CD22357A
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AC TIMING
Frequency of Master Clocks
1/t
PM
Depends on the Device Used
and the BCLK
R
/CLKSEL Pin
-
1.536
-
MHz
-
1.544
-
MHz
MCLK
X
and MCLK
R
-
2.048
-
MHz
Width of Master Clock High
t
WMH
MCLK
X
and MCLK
R
160
-
-
ns
Width of Master Clock Low
t
WML
MCLK
X
and MCLK
R
160
-
-
ns
Rise Time of Master Clock
t
RM
MCLK
X
and MCLK
R
-
-
50
ns
Fall Time of Master Clock
t
FM
MCLK
X
and MCLK
R
-
-
50
ns
Set-up Time from BCLK
X
High
(and FS
X
in Long Frame Sync
Mode) to MCLK
X
Falling Edge
t
SBFM
First Bit Clock after the Leading
Edge of FS
X
100
-
-
ns
Period of Bit Clock
t
PB
485
488
15,725
ns
Width of Bit Clock High
t
WBH
V
IH
= 2.2V
160
-
-
ns
Width of Bit Clock Low
t
WBL
V
IL
= 0.6V
160
-
-
ns
Rise Time of Bit Clock
t
RB
t
PB
= 488ns
-
-
50
ns
Fall Time of Bit Clock
t
FB
t
PB
= 488ns
-
-
50
ns
Hold Time from Bit Clock Low to
Frame Sync
t
HBF
Long Frame Only
0
-
-
ns
Hold Time from Bit Clock High to
Frame Sync
t
HOLD
Short Frame Only
0
-
-
ns
Set-up Time from Frame Sync to
Bit Clock Low
t
SFB
Long Frame Only
80
-
-
ns
Delay Time from BCLK
X
High to
Data Valid
t
DBD
Load = 150pF plus 2 LSTTL
Loads
0
-
180
ns
Delay Time to TS
X
Low
t
XDP
Load = 150pF plus 2 LSTTL
Loads
-
-
140
ns
Delay Time from BCLK
X
Low or
FS
X
Low to Data Output Disabled
t
DZC
50
-
165
ns
Delay Time to Valid Data from
FS
X
orBCLK
X
,WhicheverComes
Later
t
DZF
C
L
= 0pF to 150pF
20
-
165
ns
Set-up Time from D
R
Valid to
BCLK
R/X
Low
t
SDB
50
-
-
ns
Hold Time from BCLK
R/X
Low to
D
R
Invalid
t
HBD
50
-
-
ns
Set-up Time from FS
X/R
to
BCLK
X/R
Low
t
SF
Short Frame Sync Pulse
(1 or 2 Bit Clock Periods Long)
(Note 1)
50
-
-
ns
Hold Time from BCLK
X/R
Low to
FS
X/R
Low
t
HF
Short Frame Sync Pulse
(1 or 2 Bit Clock Periods Long)
(Note 1)
100
-
-
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD22357A | CMOS Single-Chip, Full-Feature PCM CODEC |
| CD22357AE | CMOS Single-Chip, Full-Feature PCM CODEC |
| CD22402 | Sync Generator for TV Applications and Video Processing Systems |
| CD22402D | R8C Series, 23 Group, WDTO 48P6Q-A |
| CD22402E | Sync Generator for TV Applications and Video Processing Systems |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD22354AE WAF | 制造商:Harris Corporation 功能描述: |
| CD22354E | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD22357A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Single-Chip, Full-Feature PCM CODEC |
| CD22357AE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| CD22357AE WAF | 制造商:Harris Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。