參數(shù)資料
型號(hào): CC2420DK
廠商: Electronic Theatre Controls, Inc.
英文描述: LC2MOS 5 O RON SPST Switch; Package: PDIP; No of Pins: 16; Temperature Range: Industrial
中文描述: 2.4 GHz IEEE 802.15.4標(biāo)準(zhǔn)/ ZigBee功能的RF收發(fā)器
文件頁(yè)數(shù): 33/87頁(yè)
文件大小: 1418K
代理商: CC2420DK
SmartRF
CC2420
Transmit mode
During transmit, the
FIFO
and
FIFOP
pins
are still only related to the RXFIFO. The
SFD
pin
is
however
transmission of a data frame, as shown in
Figure 14.
active during
The
SFD
pin goes high when the SFD field
has been completely transmitted. It goes
low again when the complete MPDU (as
defined by the length field) has been
transmitted or if an underflow is detected.
See the RF Data Buffering section on
page 37 for more information on TXFIFO
underflow.
As can be seen from comparing Figure 12
and Figure 14, the
SFD
pin behaves very
similarly during reception and transmission
of a data frame. If the
SFD
pins of the
transmitter and the receiver are compared
during the transmission of a data frame, a
small delay of approximately 2 μs can be
seen because of bandwidth limitations in
both the transmitter and the receiver.
Preamble
SFD
Length
Data transmitted
over RF
SFD Pin
SFDtansmted
byTXundefow
MAC Protocol Data Unit (MPDU)
STXON
command
12 symbol periods
Automatically generated
preamble and SFD
Data fetched
from TXFIFO
CRC generated
by
CC2420
Figure 14. Pin activity example during transmit
General control and status pins
In receive mode, the
FIFOP
pin can be
used to interrupt the microcontroller when
a threshold has been exceeded or a
complete frame has been received. This
pin should then be connected to a
microcontroller interrupt pin.
In receive mode, the
FIFO
pin can be
used to detect if there is data at all in the
receive
FIFO
.
The
SFD
pin can be used to extract the
timing information of transmitted and
received data frames. The
SFD
pin will go
high when a start of frame delimiter has
been completely detected / transmitted.
The
SFD
pin should preferably be
connected to a timer capture pin on the
microcontroller.
For debug purposes, the
SFD
and
CCA
pins can be used to monitor several status
signals as selected by the
IOCFG1
register. See Table 12 and Table 13 for
available signals.
The polarity of
FIFO
,
FIFOP
,
SFD
and
CCA
can be controlled by the
IOCFG0
register
(address 0x1C).
Demodulator, Symbol Synchroniser and Data Decision
The block diagram for the
CC2420
demodulator is shown in Figure 15.
Channel filtering and frequency offset
compensation is performed digitally. The
signal level in the channel is estimated to
generate the RSSI level (see the RSSI /
Energy Detection section on page 47 for
more information). Data filtering is also
included for enhanced performance.
With the ±40 ppm frequency accuracy
requirement from [1], a compliant receiver
must be able to compensate for up to 80
ppm or 200 kHz. The
CC2420
demodulator
tolerates up to 300 kHz offset without
significant degradation of the receiver
performance.
Soft decision is used at the chip level, i.e.
the demodulator does not make a decision
for each chip, only for each received
symbol. De-spreading is performed using
over sampled symbol correlators. Symbol
synchronisation
is
achieved
by
a
Chipcon AS
SmartRF
CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09
Page 33 of 87
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