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參數(shù)資料
| 型號(hào)： | CB664EY |
| 英文描述： | SEVEN DISTRIBUTED-OUTPUT CLOCK DRIVER|SSOP|16PIN|PLASTIC |
| 中文描述： | SEVEN公司分布式輸出時(shí)鐘驅(qū)動(dòng)器| SSOP封裝| 16PIN |塑料 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 53K |
| 代理商： | CB664EY |
CB664
I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM
Approved Product
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07024 Rev. **
5/6/99
Page 3 of 8
2-Wire I
2
C Control Interface
The 2-wire control interface implements a write only slave interface. The device control be read back. Sub-
addressing is not supported, thus, all preceding bytes must be sent in order to change one of the control bytes.
The 2-wire control interface allows each clock output to be individually enabled or disabled.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when
SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used
to indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the
end of data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated.
The first byte of a transfer cycle is a 7-bit address with a read /write bit as the LSB. Data is being transferred MSB
first.
The device respond to writes to 10 bytes (max) of data to address
D2
by generating the acknowledge (low) signal
on the SDATA wire following reception of each byte. The device will not respond to any other control interface
conditions.
Control Signal Registers
Note
: The pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is
activated.
Following the acknowledge of the Address Byte (
D2)
two additional bytes must be sent:
1.
“
Command Code”
byte and
2.
“Byte Count”
byte
Although the data (bits) in these two bytes are considered “ don’t care”, they must be sent and will be
acknowledge.
After the Command Code and the Count bytes have been acknowledge, the below described sequence (Byte0,
Byte1, Byte2…) will be valid and acknowledged.
Byte 0
: (1= Enable, 0= stopped)
Bit
@Pup
Pin #
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
See application note AN664-01 for further reducing power
consumption with I
C
Byte 1:
(1= Enable, 0= stopped)
Bit
@Pup
Pin #
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Description
SDR2(Enable =1,stopped=0)
Reserved
Reserved
Reserved
SDR1(Enable =1,stopped=0)
SDR0(Enable =1,stopped=0)
Reserved
Reserved
6
-
-
-
3
2
-
-
Description
16
15
-
-
12
11
-
-
SDR6 (enable=1,s topped=0)
SDR5 (enable=1, stopped=0 )
Reserved
Reserved
SDR4 (enable=1, stopped=0)
SDR3 (enable=1, stopped=0)
Reserved
Reserved
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