參數(shù)資料
型號： CB664EY
英文描述： SEVEN DISTRIBUTED-OUTPUT CLOCK DRIVER|SSOP|16PIN|PLASTIC
中文描述： SEVEN公司分布式輸出時鐘驅(qū)動器| SSOP封裝| 16PIN |塑料
文件頁數(shù)： 2/8頁
文件大?。?/td> 53K
代理商： CB664EY
CB664
I2C Clock Distribution Buffer for Three Banks of Mobile SDRAM
Approved Product
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07024 Rev. **
5/6/99
Page 2 of 8
Pin Description
Pin No.
Pin Name
PWR
I/O
Type
Description
5
CLKIN
VDD
I
PAD
This pin is connected to the input reference clock.
This clock be in the range of 10.0 to 100.0 MHz
Low Skew output clock.
Serial data of I
2
C-wire control interface. Has internal
pull-up resistor.
Serial data of I
2
C-wire control interface. Has internal
pull-up resistor
COMMON Ground
Power for output clock buffers and core logic
2,3,6,11,12,15,16
SDR(0:6)
VDD
O
BUF1
8
SDATA
-
I/O
PAD
9
SCLK
-
I
PAD
4,10,14
1,7,13
VSS
VDD
-
-
-
-
-
-
Maximum Ratings
Maximum Input Voltage Relative to VSS: VSS – 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
0
o
to +125
o
C
0
o
to +70
o
C
7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
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