VCC
參數(shù)資料
型號: CAT5132ZI-50-G
廠商: ON Semiconductor
文件頁數(shù): 7/12頁
文件大?。?/td> 0K
描述: IC POT DPP 15V 128TAP I2C 10MSOP
標準包裝: 96
接片: 128
電阻(歐姆): 50k
電路數(shù): 1
溫度系數(shù): 標準值 300 ppm/°C
存儲器類型: 非易失
接口: I²C(設備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 10-MSOP
包裝: 管件
CAT5132
http://onsemi.com
4
Table 7. A.C. CHARACTERISTICS
Symbol
Parameter (see Figure 6)
VCC = 2.7 5.5 V
Units
Min
Max
FSCL
Clock Frequency
400
kHz
TI (Note 11)
Noise Suppression Time Constant at SCL & SDA Inputs
50
ns
tAA
SLC Low to SDA Data Out and ACK Out
1
ms
tBUF (Note 11) Time the bus must be free before a new transmission can start
1.2
ms
tHD:STA
Start Condition Hold Time
0.6
ms
tLOW
Clock Low Period
1.2
ms
tHIGH
Clock High Period
0.6
ms
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
0.6
ms
tHD:DAT
Data in Hold Time
0
ns
tR (Note 11)
SDA and SCL Rise Time
0.3
ms
tF (Note 11)
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Conditions Setup Time
0.6
ms
tDH
Data Out Hold Time
100
ns
11. This parameter is tested initially and after a design or process change that affects the parameter.
Table 8. POWER UP TIMING (Notes 12, 13)
Symbol
Parameter
Min
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Table 9. WIPER TIMING
Symbol
Parameter
Min
Max
Units
tWRPO
Wiper Response Time After Power Supply Stable
5
10
ms
tWRL
Wiper Response Time After Instruction Issued
5
10
ms
Table 10. WRITE CYCLE LIMITS
Symbol
Parameter
Min
Max
Units
tWR
Write Cycle Time (see Figure 7)
5
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
Table 11. RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
NEND (Note 12)
Endurance
MILSTD883, Test Method 1033
100,000
Cycles
TDR (Note 12)
Data Retention
MILSTD883, Test Method 1008
100
Years
12.This parameter is tested initially and after a design or process change that affects the parameter.
13.tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
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