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參數(shù)資料
| 型號： | CAT5132ZI-50-G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DPP 15V 128TAP I2C 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 接片： | 128 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
CAT5132
http://onsemi.com
8
DEVICE DESCRIPTION
Access Control Register
The volatile register WCR and the non-volatile register
DR are accessed only by addressing the volatile Access
Register AR first, using the 3 byte I2C protocol for all read
and write operations (see Table 12). The first byte is the slave
address/instruction byte (see details below). The second
byte contains the address (02h) of the AR register. The data
in the third byte controls which register WCR (80h) or DR
(00h) is being addressed (see Figure 10).
Slave Address Instruction Byte Description
The first byte sent to the CAT5132 from the master
processor is called the Slave Address Byte. The most
significant five bits of the slave address are a device type
identifier. For the CAT5132 these bits are fixed at 01010
(refer to Table 13).
The next two bits, A1 and A0, are the internal slave
address and must match the physical device address which
is defined by the state of the A1 and A0 input pins. Only the
device with slave address matching the input byte will be
accessed by the master. This allows up to 4 devices to reside
on the same bus. The A1 and A0 inputs can be actively
driven by CMOS input signals or tied to VCC or Ground.
The last bit is the READ/WRITE bit and determines the
function to be performed. If it is a “1” a read command is
initiated and if it is a “0” a write is initiated. For the AR
register only write is allowed.
After the Master sends a START condition and the slave
address byte, the CAT5132 monitors the bus and responds
with an acknowledge when its address matches the
transmitted slave address.
Table 12. ACCESS CONTROL REGISTER
0
00
0
ST
1
1A
0
1
0
A
A SP
0
00
0
00
0
ST
1
1A
0
1
0
A
A SP
1
0
00
ACK
ST
OP
ACK
ST
AR
T
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
1st byte
2nd byte
AR address 02h
3rd byte
WCR(80h) / DR(00h) selection
Table 13. BYTE 1 SLAVE ADDRESS AND INSTRUCTION BYTE
Device Type Identifier
Slave Address
ID4
(MSB)
0
ID3
1
ID2
0
ID1
1
ID0
0
A1
X
A0
XX
R/W
Read/Write
(LSB)
Figure 10. Access Register Addressing Using 3 Bytes
& INSTRUCTION
S
C
P
BUS ACTIVITY:
MASTER
SDA LINE
S
R
T
FIXED
VARIABLE
AR REGISTER
ADDRESS
K
A
C
K
A
C
K
A
T
O
S
T
A
ADDRESS
SLAVE
WCR/DR
SELECTION
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