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參數(shù)資料
| 型號： | CAT5132ZI-00-GT3 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DIGITL 100K 128TAP 10MSOP |
| 標(biāo)準包裝： | 1 |
| 接片： | 128 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準值 300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 標(biāo)準包裝 |
| 產(chǎn)品目錄頁面： | 806 (CN2011-ZH PDF) |
| 其它名稱： | CAT5132ZI-00-GT3DKR |
CAT5132
http://onsemi.com
9
Wiper Control Register (WCR) Description
The CAT5132 contains a 7-bit Wiper Control Register
which is decoded to select one of the 128 switches along its
resistor array. The WCR is a volatile register and is written
with the contents of the nonvolatile Data Register (DR) on
power-up. The Wiper Control Register loses its contents
when the CAT5132 is powered-down. The contents of the
WCR may be read or changed directly by the host using a
READ/WRITE command after addressing the WCR (see
Table 12 to access WCR). Since the CAT5132 will only
make use of the 7 LSB bits (The first data bit, or MSB, is
ignored) on write instructions and will always come back as
a “0” on read commands.
A write operation (see Table 14) requires a Start condition,
followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the
three bytes the CAT5132 responds with an acknowledge. At
this time the data is written only to volatile registers, then the
device enters its standby state.
Table 14. WCR WRITE OPERATION
0
00
0
ST
1
1A
0
1
0
A
A SP
1
0
00
ACK
ST
OP
ACK
ST
AR
T
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
1st byte
2nd byte
AR address 02h
3rd byte
WCR(80h) selection
0
00
0
ST
1
1A
0
A
A SP
x
xx
ACK
ST
OP
ACK
ST
AR
T
slave address byte
WCR address 00h
data byte
An increment operation (see Table 15) requires a Start
condition, followed by a valid increment address byte
(01011), a valid address byte 00h. After each of the two
bytes, the CAT5132 responds with an acknowledge. At this
time if the data is high then the wiper is incremented or if the
data is low the wiper is decremented at each clock. Once the
stop is issued then the device enters its standby state with the
WCR data as being the last inc/dec position. Also, the wiper
position does not roll over but is limited to min and max
positions.
Table 15. WCR INCREMENT/DECREMENT OPERATION
0
00
0
ST
1
1A
0
1
0
A
A SP
1
0
00
ACK
ST
OP
ACK
ST
AR
T
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
1st byte
2nd byte
AR address 02h
3rd byte
WCR(80h) selection
0
01
0
ST
1
1A
0
A
SP
1
00
ST
OP
ACK
ST
AR
T
slave address byte
WCR address 00h
increment (1) / decrement (0) bits
A read operation (see Table 16) requires a Start condition,
followed by a valid slave address byte for write, a valid
address byte 00h, a second START and a second slave
address byte for read. After each of the three bytes, the
CAT5132 responds with an acknowledge and then the
device transmits the data byte. The master terminates the
read operation by issuing a STOP condition following the
last bit of Data byte.
Table 16. WCR READ OPERATION
0
00
0
ST
1
1A
0
1
0
A
A SP
1
0
00
ACK
ST
OP
ACK
ST
AR
T
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
1st byte
2nd byte
AR address 02h
3rd byte
WCR(80h) selection
0
00
0
ST
1
1A
0
ACK
ST
AR
T
slave address byte
WCR address 00h
0
00
0
1
ST
1
1A
0
X
SP
ST
OP
ST
AR
T
slave address byte
data byte
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