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參數(shù)資料
| 型號： | CAT5132ZI-00-GT3 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DIGITL 100K 128TAP 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接片： | 128 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 806 (CN2011-ZH PDF) |
| 其它名稱： | CAT5132ZI-00-GT3DKR |
CAT5132
http://onsemi.com
7
SERIAL BUS PROTOCOL
The following defines the features of the I2C bus protocol:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
The device controlling the transfer is a master, typically a
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5132 will be considered a slave device
in all applications.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT5132 monitors the SDA and
SCL lines and will not respond until this condition is met
(see Figure 8).
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition (see Figure 8).
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data (see Figure 9).
The CAT5132 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8-bit
byte.
When the CAT5132 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5132 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the STOP condition is
issued to indicate the end of the write operation, the
CAT5132 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the START
condition followed by the slave address. If the CAT5132 is
still busy with the write operation, no ACK will be returned.
If the CAT5132 has completed the write operation, an ACK
will be returned and the host can then proceed with the next
instruction operation.
Figure 8. Start/Stop Condition
SDA
SCL
START
CONDITION
STOP
CONDITION
Figure 9. Acknowledge Condition
START
SCL FROM
MASTER
ACK SETUP ( tSU:DAT)
BUS RELEASE DELAY (RECEIVER)
9
8
ACK DELAY ( tAA)
1
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
BUS RELEASE DELAY (TRANSMITTER)
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| CAT5132ZI-50-G | 功能描述:數(shù)字電位計(jì) IC DPP 15V 128 taps I2C RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
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| CAT5133ZGI-10 | 制造商:Catalyst Semiconductor 功能描述: |
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