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參數(shù)資料
| 型號： | CAT35C804A |
| 英文描述： | 4K-Bit Secure Access Serial E2PROM |
| 中文描述： | 4K的位安全接入串行E2PROM |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 88K |
| 代理商： | CAT35C804A |
Preliminary
CAT35C804A
7
Doc. No. 25043-00 2/98
also go to the high impedance state if an error condition
is detected. In the event an ENABLE BUSY instruction
has not been sent, a READ STATUS register instruction
can be executed. This also tells the user whether the part
is in a program/erase cycle or an error condtion. When
the device is in a program/erase cycle it will output an
8-bit status word. If it does not, it is in an error condition.
PE
The Parity Enable pin is a TTL compatible input. If the PE
pin is set HIGH, the device will be configured to commu-
nicate using even parity, and if the pin is set LOW, it will
use no parity. In this case, instructions or data that
include parity bits will not be interpreted correctly. Note:
The PE input is internally pulled down to GND (i.e.
default = no parity). As with all CMOS devices, CS, CLK
and DI inputs must be connected to either HIGH or LOW,
and not left floating.
ERR
The Error indication pin is an open drain output. If either
an instruction or parity error exists, the ERR pin will
output a “0” until the device is reset. This can be done by
pulsing CS LOW.
Figure 6. Read Timing (x8 Format)
CS
DI
HIGH-Z
DO
OP0–OP7
OP CODE
A8–A15
ADDRESS
A0–A7
ADDRESS
D0–D7
DATA
CLK
VCC
35C804 F09
Figure 7. Read Timing (x16 Format)
CS
DI
HIGH-Z
DO
OP0–OP7
OP CODE
A0–A7
ADDRESS
D8–D15
DATA
CLK
VCC
D0–D7
DATA
HIGH-Z
35C804 F10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT35C804ACI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial EEPROM |
| CAT35C804ADI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial EEPROM |
| CAT35C804AJATE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:4K-Bit Secure Access Serial E2PROM |
| CAT35C804AJITE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:4K-Bit Secure Access Serial E2PROM |
| CAT35C804AJI-TE13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial EEPROM |
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