參數(shù)資料
型號(hào): CAT34TS02VP2GT4A
廠商: ON Semiconductor
文件頁(yè)數(shù): 17/21頁(yè)
文件大?。?/td> 194K
描述: IC TEMP SENSOR 2K MEMORY 8TDFN
標(biāo)準(zhǔn)包裝: 1
功能: 溫度監(jiān)控系統(tǒng)(傳感器)
傳感器類(lèi)型: 內(nèi)部
感應(yīng)溫度: -20°C ~ 125°C
精確度: ±3°C
拓?fù)洌?/td> ADC,比較器,寄存器庫(kù)
輸出類(lèi)型: 2 線串行,I²C?/SMBUS?
輸出警報(bào):
輸出風(fēng)扇: 無(wú)
電源電壓: 3 V ~ 3.6 V
工作溫度: -20°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 8-TDFN(2x3)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱(chēng): CAT34TS02VP2GT4AOSDKR
CAT34TS02
http://onsemi.com
17
Register Data Format
The values used in the temperature data register and the 3
temperature trip point registers are expressed in twos
complement format. The measured temperature value is
expressed with 12bit resolution, while the 3 trip
temperature limits are set with 10bit resolution. The total
temperature range is arbitrarily defined as 256癈, thus
yielding an LSB of 0.0625癈 for the measured temperature
and 0.25癈 for the 3 limit values. Bit B12 in all temperature
registers represents the sign, with a 0 indicating a positive,
and a 1 a negative value. In twos complement format,
negative values are obtained by complementing their
positive counterpart and adding a 1, so that the sum of
opposite signed numbers, but of equal absolute value, adds
up to zero.
Note that trailing 0 bits, are 0 irrespective of polarity.
Therefore the dont care bits (B1 and B0) in the 10bit
resolution temperature limit registers, are always 0.
Table 16. 12BIT TEMPERATURE DATA FORMAT
Binary (B12 to B0)
Hex
Temperature
1 1100 1001 0000
1C90
55癈
1 1100 1110 0000
1CE0
50癈
1 1110 0111 0000
1E70
25癈
1 1111 1111 1111
1FFF
0.0625癈
0 0000 0000 0000
000
0癈
0 0000 0000 0001
001
+0.0625癈
0 0001 1001 0000
190
+25癈
0 0011 0010 0000
320
+50癈
0 0111 1101 0000
7D0
+125癈
Event Pin Functionality
The EVENT
  output reacts to temperature changes as
illustrated in Figure 33, and according to the operating mode
defined by the Configuration register.
In Interrupt Mode, the enabled EVENT
 output will be
asserted every time the temperature crosses one of the alarm
window limits, and can be deasserted by writing a 1 to the
clear event bit (B5) in the configuration register. Once the
temperature exceeds the critical limit, the EVENT
 remains
asserted as long as the temperature stays above the critical
limit and cannot be cleared. A clear request sent to the
CAT34TS02 while the temperature is above the critical limit
will be acknowledged, but will be executed only after the
temperature drops below the critical limit.
In Comparator Mode, the EVENT
 output is asserted
outside the alarm window limits, while in Critical
Temperature Mode, EVENT
 is asserted only above the
critical limit. Clear requests are ignored in this mode. The
exact trip limits are determined by the 3 temperature limit
settings and the hysteresis offsets, as illustrated in Figure 34.
Following a TS shutdown request, the converter is
stopped and the most recently recorded temperature value
present in the TDR is frozen; the EVENT
 output will continue
to reflect the state immediately preceding the shutdown
command. Therefore, if the state of the EVENT
  output
creates an undesirable bus condition, appropriate action must
be taken either before or after shutting down the TS. This may
require clearing the event, disabling the EVENT
 output or
perhaps changing the EVENT
 output polarity.
In normal use, events are triggered by a change in
recorded temperature, but the CAT34TS02 will also respond
to limit register changes. Whereas recorded temperature
values are updated at sampling rate frequency, limits can be
modified at any time. The enabled EVENT
 output will react
to limit changes as soon as the respective registers are
updated. This feature may be useful during testing.
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