參數(shù)資料
型號: CAT34TS02VP2GT4A
廠商: ON Semiconductor
文件頁數(shù): 13/21頁
文件大?。?/td> 194K
描述: IC TEMP SENSOR 2K MEMORY 8TDFN
標(biāo)準(zhǔn)包裝: 1
功能: 溫度監(jiān)控系統(tǒng)(傳感器)
傳感器類型: 內(nèi)部
感應(yīng)溫度: -20°C ~ 125°C
精確度: ±3°C
拓?fù)洌?/td> ADC,比較器,寄存器庫
輸出類型: 2 線串行,I²C?/SMBUS?
輸出警報:
輸出風(fēng)扇:
電源電壓: 3 V ~ 3.6 V
工作溫度: -20°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-TDFN(2x3)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: CAT34TS02VP2GT4AOSDKR
CAT34TS02
http://onsemi.com
13
Temperature Sensor Operation
The TS component in the CAT34TS02 combines a
Proportional to Absolute Temperature (PTAT) sensor with
a SD modulator, yielding a 12 bit plus sign digital
temperature representation.
The TS runs on an internal clock, and starts a new
conversion cycle at least every 100 ms. The result of the
most recent conversion is stored in the Temperature Data
Register (TDR),  and  remains  there  following  a  TS
ShutDown. Reading from the TDR does not interfere with
the conversion cycle.
The value stored in the TDR is compared against limits
stored in the High Limit Register (HLR), the Low Limit
Register (LLR)  and/or  Critical Temperature Register
(CTR). If the measured value is outside the alarm limits or
above the critical limit, then the EVENT
  pin may be
asserted. The EVENT
 output function is programmable, via
the Configuration Register for interrupt mode, comparator
mode and polarity.
The temperature limit registers can be Read or Written by
the host, via the serial interface. At poweron, all the
(writable) internal registers default to 0x0000, and should
therefore be initialized by the host to the desired values. The
EVENT
  output starts out disabled (corresponding to
polarity active low); thus preventing irrelevant event bus
activity before the limit registers are initialized. While the
TS is enabled (not shutdown), event conditions are
normally generated by a change in measured temperature as
recorded in the TDR, but limit changes can also trigger
events as soon as the new limit creates an event condition,
i.e. asynchronously with the temperature sampling activity.
In order to minimize the thermal resistance between
sensor and PCB, it is recommended that the exposed
backside die attach pad (DAP) be soldered to the PCB
ground plane.
Registers
The CAT34TS02 contains eight 16bit wide registers
allocated to TS functions, as shown in Table 9. Upon
powerup, the internal address counter points to the
capability register.
Capability Register (User Read Only)
This register lists the capabilities of the TS, as detailed in
the corresponding bit map.
Configuration Register (Read/Write)
This register controls the various operating modes of the
TS, as detailed in the corresponding bit map.
Temperature Trip Point Registers (Read/Write)
The CAT34TS02 features 3 temperature limit registers,
the HLR, LLR and CLR mentioned earlier. The
temperature value recorded in the TDR is compared to the
various limit values, and the result is used to activate the
EVENT
 pin. To avoid undesirable EVENT
 pin activity, this
pin is automatically disabled at powerup to allow the host
to initialize the limit registers and the converter to complete
the first conversion cycle under nominal supply conditions.
Data format is twos complement with the LSB representing
0.25癈, as detailed in the corresponding bit maps.
Temperature Data Register (User Read Only)
This register stores the measured temperature, as well as
trip status information. B15, B14, and B13 are the trip status
bits, representing the relationship between measured
temperature and the 3 limit values; these bits are not affected
by EVENT status or by Configuration register settings
regarding   EVENT
   pin.   Measured   temperature   is
represented by bits B12 to B0. Data format is twos
complement, where B12 represents the sign, B11 represents
128癈, etc. and B0 represents 0.0625癈.
Manufacturer ID Register (Read Only)
The manufacturer ID assigned by the PCISIG trade
organization to the CAT34TS02 device is fixed at 0x1B09.
Device ID and Revision Register (Read Only)
This register contains manufacturer specific device ID
and device revision information.
Table 9. THE TS REGISTERS
Register Address
Register Name
PowerOn Default
Read/Write
0x00
Capability Register
0x007F
Read
0x01
Configuration Register
0x0000
Read/Write
0x02
High Limit Register
0x0000
Read/Write
0x03
Low Limit Register
0x0000
Read/Write
0x04
Critical Limit Register
0x0000
Read/Write
0x05
Temperature Data Register
Undefined
Read
0x06
Manufacturer ID Register
0x1B09
Read
0x07
Device ID/Revision Register
Rev. B
0x0813
Read
Rev. C
0x0A00
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