- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374140 > CAT33C804APA-TE13 4K-Bit Secure Access Serial E2PROM PDF資料下載
參數(shù)資料
| 型號： | CAT33C804APA-TE13 |
| 英文描述： | 4K-Bit Secure Access Serial E2PROM |
| 中文描述： | 4K的位安全接入串行E2PROM |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 89K |
| 代理商： | CAT33C804APA-TE13 |
Preliminary
CAT33C804A
6
Doc. No. 25044-00 2/98
CLK
The System Clock is a TTL compatible input pin that
allows operation of the device at a specified frequency.
The CAT33C804A is designed with an internal divider to
produce a 9600 baud output for an input clock frequency
of 4.9152 MHz.
DI
The Data Input pin is TTL compatible and accepts data
and instructions in a serial format. Each byte must begin
with “0” as a start bit. The device will accept as many
bytes as an instruction requires, including both data and
address bytes. Extra bits will be disregarded if they are
“1”s and extra “0”s will be misinterpreted as the start bit
of the next instruction. An instruction error will cause the
device to abort operation and all I/O communication will
be terminated until a reset is received.
DO
The Data Output pin is a tri-state TTL compatible output.
It is normally in a high impedance state unless a READ
or an ENABLE BUSY instruction is executed. Following
the completion of a 16-bit or 8-bit data stream, the output
will return to the high impedance state. During a pro-
gram/erase cycle, if the ENABLE BUSY instruction has
been previously executed, the output will stay LOW
while the device is BUSY, and it will be set HIGH when
the program/erase cycle is completed. DO will stay
HIGH until the completion of the next instruction’s op-
code and, if the next instruction is a READ, DO will output
the appropriate data at the end of the instruction. If the
ENABLE BUSY instruction has not been previously
executed, DO will stay in a high impedance state. DO will
CS
DI
HIGH-Z
DO
OP0–OP7
tEW
BUSY(1)
OP CODE
A8–A15
ADDRESS
A0–A7
ADDRESS
D0–D7
DATA
Figure 5. Program/Erase Timing (x16 Format)
Figure 4. Program/Erase Timing (x8 Format)
33C804 F07
CS
DI
HIGH-Z
DO
OP0–OP7
tEW
BUSY(1)
OP CODE
A0–A7
ADDRESS
D8–D15
DATA
D0–D7
DATA
33C804 F08
Note:
(1) DO becomes low to indicate busy status if ENBSY was previously executed. If ENBSY was not previously executed, DO will be in the
High-Z condition.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CAT33C804API-TE13 | 4K-Bit Secure Access Serial E2PROM |
| CAT35C104I | 4K-Bit SERIAL E2PROM |
| CAT35C804A | 4K-Bit Secure Access Serial E2PROM |
| CAT37 | CMOS White LED Driver Boost Converter |
| CAT37EKK-TE7 | CMOS White LED Driver Boost Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT33C804APITE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:4K-Bit Secure Access Serial E2PROM |
| CAT33C804API-TE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:4K-Bit Secure Access Serial E2PROM |
| CAT33C804APTE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:4K-Bit Secure Access Serial E2PROM |
| CAT33C804AP-TE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:4K-Bit Secure Access Serial E2PROM |
| CAT33C804BCI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial EEPROM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。