參數(shù)資料
型號(hào): CAT25C16VA-TE13
元件分類: PROM
英文描述: 2K X 8 SPI BUS SERIAL EEPROM, PDSO8
封裝: LEAD FREE AND HALOGEN FREE, SOIC-8
文件頁數(shù): 12/12頁
文件大?。?/td> 77K
代理商: CAT25C16VA-TE13
9
CAT25C01/02/04/08/16
Doc. No. 1016, Rev. N
Figure 7. WRSR Timing
Note: Dashed Line= mode (1, 1) – ––––
0
1
2
345
67
8
10
911
12
13
14
SCK
SI
MSB
HIGH IMPEDANCE
DATA IN
15
SO
CS
7
6
5
4
3
2
10
00
0
00
0
1
OPCODE
DESIGN CONSIDERATIONS
The CAT25C01/02/04/08/16
powers up in a write
disable state and in a low power standby mode. A
WREN instruction must be issued to perform any writes
to the device after power up. Also,on power up
CS
should be brought low to enter a ready state and
receive an instruction. After a successful byte/page
write or status register write, the CAT25C01/02/04/08/
16 goes into a write disable mode.
CS must be set high
after the proper number of clock cycles to start an
internal write cycle. Access to the array during an
internal write cycle is ignored and programming is
continued. On power up, SO is in a high impedance. If
an invalid op code is received, no data will be shifted
into the CAT25C01/02/04/08/16, and the serial output
pin (SO) will remain in a high impedance state until the
falling edge of
CS is detected again.
When powering down, the supply should be taken down
to 0V, so that the CAT25C01/02/04/08/16 will be reset
when power is ramped back up. If this is not possible,
then, following a brown-out episode, the CAT25C01/
02/04/08/16 can be reset by refreshing the contents of
the Status Register (See Application Note AN10).
Figure 8. Page Write Instruction Timing
Note: Dashed Line= mode (1, 1) – ––––
SK
SI
SO
00
X*
0
1
0
Data
Byte 1
012345678
21
22
23 24-31
32-39
Data
Byte 2
Data
Byte 3
Data Byte N
CS
OPCODE
7..1
0
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
DATA IN
HIGH IMPEDANCE
BYTE ADDRESS*
*Please check the Byte Address Table.
AN
A0
*X = 0 for CAT25C01, CAT25C02, CAT25C08 and CAT25C16; X = A8 for CAT25C04.
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