參數(shù)資料
型號(hào): CAT25C16VA-TE13
元件分類(lèi): PROM
英文描述: 2K X 8 SPI BUS SERIAL EEPROM, PDSO8
封裝: LEAD FREE AND HALOGEN FREE, SOIC-8
文件頁(yè)數(shù): 11/12頁(yè)
文件大小: 77K
代理商: CAT25C16VA-TE13
8
CAT25C01/02/04/08/16
Doc. No. 1016, Rev. N
SK
SI
SO
00
X*
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
012345678
21
22
23
24
25
26
27
28
29
30
31
CS
OPCODE
DATA IN
HIGH IMPEDANCE
BYTE ADDRESS*
**
AN
A0
*Please check the Byte Address Table
X = 0 for CAT25C01, CAT25C02 and CAT25C08, CAT25C16; X = A8 for CAT25C04.
Figure 6. Write Instruction Timing
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the
CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C08/16. (only 10-bit addresses are
used for 25C08, 11-bit addresses are used for 25C16.
The rest of the bits are don't care bits) and 8-bit address
for 25C01/02/04 (for the 25C04, bit 3 of the read data
instruction contains address A8).
Programming will
start after the
CS is brought high. Figure 6 illustrates byte
write sequence.
During an internal write cycle, all
commands will be ignored except the RDSR (Read
Status Register) instruction.
The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction
Page Write
The CAT25C01/02/04/08/16 features page write capa-
Note: Dashed Line= mode (1, 1) – ––––
bility. After the initial byte, the host may continue to write
up to 16 bytes of data to the CAT25C01/02/04 and 32
bytes of data for 25C08/16. After each byte of data
received, lower order address bits are internally
incremented by one; the high order bits of address will
remain constant.The only restriction is that the X (X=16
for 25C01/02/04 and X=32 for 25C08/16) bytes must
reside on the same page.
If the address counter
reaches the end of the page and clock continues, the
counter will “roll over” to the first address of the page and
overwrite any data that may have been written. The
CAT25C01/02/04/08/16 is automatically returned to the
write disable state at the completion of the write cycle.
Figure 8 illustrates the page write sequence.
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
Figure 5. RDSR Instruction Timing
Note: Dashed Line= mode (1, 1) – ––––
0
1
2
345
67
8
10
911
12
13
14
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
SO
7
6
5
4
3
2
1
0
CS
00
0
00
1
0
1
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