參數(shù)資料
型號: CAT24C03VP2I-3
元件分類: EEPROM
英文描述: 2-Kb I2C CMOS Serial EEPROM with Partial Array Write Protection
中文描述: 2 KB的的CMOS串行EEPROM的I2C偏陣列寫保護
文件頁數(shù): 2/20頁
文件大?。?/td> 410K
代理商: CAT24C03VP2I-3
CAT24C03
2
Doc. No. 1113, Rev. A
2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
Voltage on Any Pin with Respect to Ground
(1)
-65°C to +150°C
-0.5 V to +6.5 V
* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS
(2)
Symbol
N
END
(*)
T
DR
Parameter
Endurance
Data Retention
Min
Units
1,000,000
100
Program/ Erase Cycles
Years
(*) Page Mode, V
CC
= 5 V, 25°C
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Max
Units
I
CC
Supply Current
Read or Write at 400 kHz
1
mA
I
SB
Standby Current
All I/O Pins at GND or V
CC
2
μ
A
I
L
I/O Pin Leakage
Pin at GND or V
CC
2
μ
A
V
IL
Input Low Voltage
-0.5
V
CC
x 0.3
V
V
IH
Input High Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output Low Voltage
V
CC
> 2.5 V, I
OL
= 3.0 mA
0.4
V
V
OL2
Output Low Voltage
V
CC
> 1.8 V, I
OL
= 1.0 mA
0.2
V
PIN IMPEDANCE CHARACTERISTICS
T
A
= 25°C, f = 400 kHz, V
CC
= 5 V
Symbol
Parameter
Conditions
Min
Max
Units
C
IN(2)
SDA I/O Pin Capacitance
V
IN
= 0 V
8
pF
C
IN(2)
Input Capacitance (other pins)
V
IN
= 0 V
6
pF
Z
WPL
WP Input Low Impedance
V
IN
< 0.5 V
5
70
k
Ω
I
LWPH
WP Input High Leakage
V
IN
> V
CC
x 0.7
2
μ
A
Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
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