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參數(shù)資料
| 型號： | CAT1027ZI-45TE13 |
| 英文描述： | Dual Voltage Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM |
| 中文描述： | 雙電壓監(jiān)控電路，帶有I2C串行的2K位CMOS EEPROM的 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 153K |
| 代理商： | CAT1027ZI-45TE13 |
12
CAT1026, CAT1027
Doc. No. 3010, Rev. K
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write opration, the
CAT1026 and CAT1027 initiate the internal write cycle.
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the device is still busy with the
write operation, no ACK will be returned. If a write
operation has completed, an ACK will be returned and
the host can then proceed with the next read or write
operation.
Read Operations
The READ operation for the CAT1026 and CAT1027 is
initiated in the same manner as the write operation with
one exception, the R/
W
bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
SCL
SDA
8TH BIT
STOP
NO ACK
DATA OUT
8
9
SLAVE
ADDRESS
S
A
C
K
DATA
N
O
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
Figure 11. Immediate Address Read Timing
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