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參數(shù)資料
| 型號(hào)： | CA5160M96 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 4MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output |
| 中文描述： | OP-AMP, 15000 uV OFFSET-MAX, 4 MHz BAND WIDTH, PDSO8 |
| 文件頁(yè)數(shù)： | 5/18頁(yè) |
| 文件大?。?/td> | 910K |
| 代理商： | CA5160M96 |
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3-5
Schematic Diagram
Application Information
Circuit Description
Refer to the block diagram of the CA5160 CMOS Operational
Amplifier. The input terminals may be operated down to 0.5V
below the negative supply rail, and the output can be swung
very close to either supply rail in many applications. Conse-
quently, the CA5160 circuit is ideal for single supply operation.
Three class A amplifier stages, having the individual gain
capability and current consumption shown in the block dia-
gram, provide the total gain of the CA5160. A biasing circuit
provides two potentials for common use in the first and sec-
ond stages. Terminals 8 and 1 can be used to supplement the
internal phase compensation network if additional phase com-
pensation or frequency roll-off is desired. Terminals 8 and 4
can also be used to strobe the output stage into a low quies-
cent current state. When Terminal 8 is tied to the negative
supply rail (Terminal 4) by mechanical or electrical means, the
output potential at Terminal 6 essentially rises to the positive
supply rail potential at Terminal 7. This condition of essentially
zero current drain in the output stage under the strobed “OFF”
condition can only be achieved when the ohmic load resis-
tance presented to the amplifier is very high (e.g., when the
amplifier output is used to drive CMOS digital circuits in com-
parator applications).
Input Stages
The circuit of the CA5160 is shown in the schematic diagram.
It consists of a differential input stage using PMOS field effect
transistors (Q
6
, Q
7
) working into a mirror pair of bipolar tran-
sistors (Q
9
, Q
10
) functioning as load resistors together with
resistors R
3
through R
6
. The mirror pair transistors also func-
tion as a differential-to-single-ended converter to provide base
drive to the second-stage bipolar transistor (Q
11
). Offset null-
ing, when desired, can be effected by connecting a 100,000
potentiometer across Terminals 1 and 5 and the potentiome-
ter slider arm to Terminal 4.
Cascode-connected PMOS transistors Q
2
, Q
4
, are the
constant current source for the input stage. The biasing
circuit for the constant current source is subsequently
described. The small diodes D
5
through D
7
provide gate-
oxide protection against high voltage transients, including
static electricity during handling for Q
6
and Q
7
.
Second Stage
Most of the voltage gain in the CA5160 is provided by the
second amplifier stage, consisting of bipolar transistor Q
11
and its cascode-connected load resistance provided by
7
4
8
1
5
2
3
BIAS CIRCUIT
“CURRENT SOURCE
LOAD” FOR Q
11
Q
2
D
1
D
2
D
3
D
4
Z
1
8.3V
R
1
40k
Q
1
Q
4
R
2
5k
INPUT STAGE
D
5
NON-INV.
INPUT
INV. INPUT
+
-
Q
6
R
3
1k
Q
9
Q
10
R
5
1k
R
6
1k
R
4
1k
Q
7
D
6
D
7
Q
3
OFFSET NULL
Q
11
SUPPLEMENTARY
COMP IF DESIRED
STROBING
SECOND
STAGE
OUTPUT
STAGE
Q
8
Q
12
Q
5
V+
2k
30
pF
6
OUTPUT
CURRENT SOURCE
FOR Q
6
AND Q
7
NOTE: Diodes D
5
through D
7
provide gate oxide protection for MOSFET Input Stage.
CA5160
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CA5160S | 制造商:HAR 功能描述:integrated circuit metal can 8 pin |
| CA5170 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CA5180 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CA51-LC | 功能描述:開發(fā)軟件 COMPILER KIT EC++ FOR 8051 MCU’S RoHS:否 制造商:Atollic Inc. 產(chǎn)品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CA51-LICLAPSE | 制造商:Keil Tools by ARM 功能描述:CA51 STANDARD LIC LAPSED 90+ DAYS |
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