參數(shù)資料
型號(hào)： CA3240E
廠商： HARRIS SEMICONDUCTOR
元件分類： 運(yùn)動(dòng)控制電子
英文描述： Dual, 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output
中文描述： DUAL OP-AMP, 15000 uV OFFSET-MAX, 4.5 MHz BAND WIDTH, PDIP8
文件頁(yè)數(shù)： 4/15頁(yè)
文件大?。?/td> 609K
代理商： CA3240E
4
Common-Mode Rejection Ratio
CMRR
32
32
μ
V/V
dB
90
90
Common-Mode Input Voltage Range (See Figure 25)
V
ICR
-0.5
-0.5
V
2.6
2.6
V
Power Supply Rejection Ratio
PSRR
31.6
31.6
μ
V/V
dB
90
90
Maximum Output Voltage (See Figures 24, 25)
V
OM
+
V
OM
-
I
OM
+
I
OM
-
SR
3
3
V
0.3
0.3
V
Maximum Output Current
Source
20
20
mA
Sink
1
1
mA
V/
μ
s
MHz
Slew Rate (See Figure 15)
7
7
Gain Bandwidth Product (See Figure 14)
f
T
I+
4.5
4.5
Supply Current (See Figure 16)
4
4
mA
Device Dissipation
P
D
20
20
mW
Electrical Specifications
For Equipment Design, at V+ = 5V, V- = 0V, T
A
= 25
o
C, Unless Otherwise Specified
(Continued)
PARAMETER
SYMBOL
TYPICAL VALUES
UNITS
CA3240A
CA3240
Test Circuits and Waveforms
FIGURE 1A. SMALL SIGNAL RESPONSE
FIGURE 1B. LARGE SIGNAL RESPONSE
FIGURE 1C. TEST CIRCUIT
FIGURE 1. SPLIT-SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT AND ASSOCIATED WAVEFORMS
50mV/Div., 200ns/Div.
Top Trace: Input, Bottom Trace: Output
5V/Div., 1
μ
s/Div.
Top Trace: Input, Bottom Trace: Output
2k
10k
CA3240
-
+15V
-15V
0.1
μ
F
0.1
μ
F
100pF
SIMULATED
LOAD
2k
0.05
μ
F
+
BW (-3dB) = 4.5MHz
SR = 9V/
μ
s
CA3240, CA3240A
相關(guān)PDF資料
PDF描述
CA3240 Dual, 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output(雙路、4.5MHz、BiMOS運(yùn)算放大器（MOSFET輸入,雙極輸出）)
CA3240A Dual, 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output(雙路、4.5MHz、BiMOS運(yùn)算放大器（MOSFET輸入,雙極輸出）)
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參數(shù)描述
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