參數(shù)資料
型號(hào)： CA3096M96
廠商： HARRIS SEMICONDUCTOR
元件分類： 小信號(hào)晶體管
英文描述： NPN/PNP Transistor Arrays
中文描述： 50 mA, 35 V, 5 CHANNEL, NPN AND PNP, Si, SMALL SIGNAL TRANSISTOR, MS-012AC
封裝： MS-012AC, 16 PIN
文件頁(yè)數(shù)： 13/14頁(yè)
文件大小： 133K
代理商： CA3096M96
13
CA3096, CA3096A, CA3096C
Dual-In-Line Plastic Packages (PDIP)
C
e
A
E
C
e
B
e
C
SEATING
PLANE
BASE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
0.010 (0.25)
C
A
M
B S
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M
-
1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS
-
3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and
are measured with the leads constrained to be perpendic-
ular to datum
.
7. e
B
and e
C
are measured at the lead tips with the leads unconstrained.
e
C
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
e
A
-C-
E16.3
(JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.15
1.77
8, 10
C
0.008
0.014
0.204
0.355
-
D
0.735
0.775
18.66
19.68
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
e
A
e
B
L
0.300 BSC
7.62 BSC
6
-
0.430
-
10.92
7
0.115
0.150
2.93
3.81
4
N
16
16
9
Rev. 0 12/93
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