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參數(shù)資料
| 型號(hào)： | CA3096M96 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 小信號(hào)晶體管 |
| 英文描述： | NPN/PNP Transistor Arrays |
| 中文描述： | 50 mA, 35 V, 5 CHANNEL, NPN AND PNP, Si, SMALL SIGNAL TRANSISTOR, MS-012AC |
| 封裝： | MS-012AC, 16 PIN |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大小： | 133K |
| 代理商： | CA3096M96 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)
12
FIGURE 39. CAPACITANCE vs BIAS VOLTAGE (PNP)
Typical Performance Curves
(Continued)
C
BIAS VOLTAGE (V)
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
9
10
C
BE
C
BI
C
BC
0
Metallization Mask Layout
CA3096H
40
30
20
10
0
40
30
20
10
0
37-45
(0.940-1.143)
4-10 (0.102-0.254)
37-45
(0.940-1.143)
Dimensions in parentheses are in millimeters and are derived from the
basic inch dimensions as indicated. Grid graduations are in mils (10
-3
inch).
The photographs and dimensions represent a chip when it is part of
the wafer. When the wafer is cut into chips, the cleavage angles are
57 degrees instead of 90 degrees with respect to the face of the chip.
Therefore, the isolated chip is actually 7mils (0.17mm) larger in both
dimensions.
CA3096, CA3096A, CA3096C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CA3096 | NPN/PNP Transistor Arrays |
| CA3096A | NPN/PNP Transistor Arrays |
| CA3096AE | HEATSHRINK POLY Q2Z 6X50FT BLK |
| CA3096AM | NPN/PNP Transistor Arrays |
| CA3096AM96 | NPN/PNP Transistor Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CA3097 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:THYRISTOR/TRANSISTOR ARRAY |
| CA3097E | 制造商:Harris Corporation 功能描述: |
| CA3097H WAF | 制造商:Harris Corporation 功能描述: |
| CA3098 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Schmitt Trigger with Memory, Dual Input Precision Level Detector |
| CA3098 WAF | 制造商:Harris Corporation 功能描述: |
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