參數(shù)資料
型號(hào)： CA3096AE
廠商： HARRIS SEMICONDUCTOR
元件分類： 小信號(hào)晶體管
英文描述： HEATSHRINK POLY Q2Z 6X50FT BLK
中文描述： 50 mA, 35 V, 5 CHANNEL, NPN AND PNP, Si, SMALL SIGNAL TRANSISTOR, MS-001-BB
封裝： MS-001BB, 16 PIN
文件頁(yè)數(shù)： 14/14頁(yè)
文件大?。?/td> 133K
代理商： CA3096AE
14
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
CA3096, CA3096A, CA3096C
Small Outline Plastic Packages (SOIC)
INDEX
AREA
E
D
N
1
2
3
-B-
0.25(0.010)
C A
M
B S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45
o
C
H
0.25(0.010)
B
M
M
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M
-
1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
M16.15
(JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
e
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
16
16
7
0
o
8
o
0
o
8
o
-
Rev. 0 12/93
相關(guān)PDF資料
PDF描述
CA3096AM NPN/PNP Transistor Arrays
CA3096AM96 NPN/PNP Transistor Arrays
CA3096C NPN/PNP Transistor Arrays
CA3096CE NPN/PNP Transistor Arrays
CA3096E NPN/PNP Transistor Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CA3096AM 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NPN/PNP Transistor Arrays
CA3096AM96 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NPN/PNP Transistor Arrays
CA3096C 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NPN/PNP Transistor Arrays
CA3096CE 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NPN/PNP Transistor Arrays
CA3096CM 制造商:Rochester Electronics LLC 功能描述:- Bulk
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