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參數(shù)資料
| 型號(hào)： | C9851BT |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大小： | 131K |
| 代理商： | C9851BT |
+/+
…when timing is critical
C9851
Clock Generator for Pentium
III Server and Workstation Applications
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
1.0
2/1/2000
MILPITAS, CA TEL 408-263-6300, FAX 408-263-6571
Page 2 of 13
http://www.imicorp.com
Pin Description
PIN No.
Pin Name
I/O
Description
8
3VMref
O
Output clock for driving the DRCG device. See table 1, page1 for frequency selection.
9
3VMref_b
O
Output clock for driving the DRCG device. See table 1, page1 for frequency selection. It
is 180 degrees out of phase (inverted) from the 3VMref clock.
23
Spread#
PU
When asserted low, this pin invokes Spread Spectrum functionality. Spread spectrum is
applicable to CPU(1:6), CPU(1:6)#, 3VMref, 3VMref_b, and 3V66 clocks. This pin has a
250K
internal Pull-up.
45,42,39,36,
33,30
CPU(1:6)
44,41,38,35,
32,29
CPU(1:6)#
O
Differential host clock outputs. These outputs are used in pairs, (CPU1-1#, CPU2-2#,
CPU3-3#, CPU4-4#, CPU5-5#, and CPU6-6#) for differential clocking of the host bus.
CPU(1:6)# are 180 degrees out of phase with their complements, CPU(1:6). See table 1,
page 1 for frequency selection.
27
I_Ref
P
This pin establishes the reference current for the internal current steering buffers of the
CPU clocks. A resistor is connected from this pin to ground to set the value of this current.
See applications data on page 9 of this data sheet for details.
14
3V66
O
Fixed 66.67 MHz clock output for driving the IMI B9852 buffer device.
24
PwrDwn#
PU
When asserted low, this pin Invokes power-down mode by shutting off all the clocks,
disabling all internal circuitry, and shutting down the crystal oscillator. The 3VMref,
3VMref_B, 3V66, REF and CPU clocks are driven low during this condition. It has a
250K
internal Pull-up.
22, 21
SelA, SelB
PD
Input select pins. See table 1, page 1. Each pin has a 250K
internal Pull-down
16
SEL100/133
PU
Input select pin. See table 1, page 1. It has a 250K
internal Pull-up
5XOUT
O
Crystal Buffer output pin. Connects to a crystal only. When an external signal other than
a crystal is used or when in Test mode, this pin is kept unconnected.
4XIN
I
Crystal Buffer input pin. Connects to a crystal, or an external single ended input clock
signal.
2
REF
O
A buffered output clock of the signal applied at Xin. Typically, 14.31818MHz.
18, 17
MultSel (0,1)
I
These input select pins configure the Ioh current (and thus the Voh swing amplitude) of
the CPU clock output pairs. Each pin has a 250K
internal Pull-up. See the table 5 for
current and resistor values.
48, 3,
VDDR
P
3.3V power supply pins for Ref clock and crystal buffer.
46,40,34,28
VDDC
P
3.3V power supply pins for CPU(1:6) / CPU(1:6)# outputs.
11, 19
VDD
P
3.3V power supply pins for common supply to the core.
13
VDDL
P
3.3V power supply pins for 3V66 output.
25
VDDI
P
3.3V power supply pins for internal current reference circuitry.
7
VDDM
P
3.3V power supply pin for 3Vmref and 3Vmref_b outputs
1, 6
VSSR
P
Ground pins for the Ref clock and crystal buffer.
31, 37, 43
VSSC
P
Ground pins for the CPU(1:6)/CPU(1:6)# outputs.
12, 20, 47
VSS
P
Ground pins for common supply to the core.
15
VSSL
P
Ground pin for the 3V66 output.
26
VSSI
P
Ground pin for internal current reference circuitry.
10
VSSM
P
Ground pin for 3Vmref and 3Vmref_b outputs.
Note: Definition of I/O column pneumonic on pin description table above:
I = Input pin, O = output pin, P = power supply pin, PU = This indicated that a bi-directional pin contains a device internal pull-up
resistor. This will insure that this pin of the device will be seen by the internal logic as a logic 1 level. Likewise pins with a PD
designation are guaranteed to be seen as a logic 0 level if no external level setting circuitry is present at power up.
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