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參數(shù)資料
| 型號： | C9851 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Clock Generator for Pentium III Server and Workstation Applications |
| 中文描述： | 時鐘奔騰III服務器和工作站發(fā)電機應用 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 122K |
| 代理商： | C9851 |
Clock Generator for Pentium
III Server and Workstation Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 2 of 14
PRELIMINARY
C9851
Pin Description
PIN No.
8
9
Pin Name
I/O
O
O
Description
Output clock for driving the DRCG device. See table 1, page1 for frequency selection.
Output clock for driving the DRCG device. See table 1, page1 for frequency selection. It
is 180 degrees out of phase (inverted) from the 3VMref clock.
When asserted low, this pin invokes Spread Spectrum functionality. Spread spectrum is
applicable to CPU(1:6), CPU(1:6)#, 3VMref, 3VMref_b, and 3V66 clocks. This pin has a
250K
internal Pull-up.
Differential host clock outputs. These outputs are used in pairs, (CPU1-1#, CPU2-2#,
CPU3-3#, CPU4-4#, CPU5-5#, and CPU6-6#) for differential clocking of the host bus.
CPU(1:6)# are 180 degrees out of phase with their complements, CPU(1:6). See table 1,
page 1 for frequency selection.
This pin establishes the reference current for the internal current steering buffers of the
CPU clocks. A resistor is connected from this pin to ground to set the value of this current.
See applications data on page 9 of this data sheet for details.
Fixed 66.67 MHz clock output for driving the IMI B9852 buffer device.
When asserted low, this pin Invokes power-down mode by shutting off all the clocks,
disabling all internal circuitry, and shutting down the crystal oscillator. The 3VMref,
3VMref_B, 3V66, REF and CPU clocks are driven low during this condition. It has a
250K
internal Pull-up.
Input select pins. See table 1, page 1. Each pin has a 250K
internal Pull-down
Input select pin. See table 1, page 1. It has a 250K
internal Pull-up
Crystal Buffer output pin. Connects to a crystal only. When an external signal other than
a crystal is used or when in Test mode, this pin is kept unconnected.
Crystal Buffer input pin. Connects to a crystal, or an external single ended input clock
signal.
A buffered output clock of the signal applied at Xin. Typically, 14.31818MHz.
These input select pins configure the LOH current (and thus the VOH swing amplitude) of
the CPU clock output pairs. Each pin has a 250K
internal Pull-up. See the table 5 for
current and resistor values.
3.3V power supply pins for Ref clock and crystal buffer.
3.3V power supply pins for CPU(1:6) / CPU(1:6)# outputs.
3.3V power supply pins for common supply to the core.
3.3V power supply pins for 3V66 output.
3.3V power supply pins for internal current reference circuitry and internal PLL.
3.3V power supply pin for 3Vmref and 3Vmref_b outputs
Ground pins for the Ref clock and crystal buffer.
Ground pins for the CPU(1:6)/CPU(1:6)# outputs.
Ground pins for common supply to the core.
Ground pin for the 3V66 output.
Ground pin for internal current reference circuitry and internal PLL.
Ground pin for 3Vmref and 3Vmref_b outputs.
Note: Definition of I/O column pneumonic on pin description table above:
I = Input pin, O = output pin, P = power supply pin, PU = This indicated that a bi-directional pin contains a device internal pull-up
resistor. This will insure that this pin of the device will be seen by the internal logic as a logic 1 level. Likewise pins with a PD
designation are guaranteed to be seen as a logic 0 level if no external level setting circuitry is present at power up.
3VMref
3VMref_b
23
Spread#
PU
45,42,39,36,
33,30
44,41,38,35,
32,29
27
CPU(1:6)
CPU(1:6)#
O
I_Ref
P
14
24
3V66
PwrDwn#
O
PU
22, 21
16
5
SelA, SelB
SEL100/133
XOUT
PD
PU
O
4
XIN
I
2
REF
O
I
18, 17
MultSel (0,1)
3
VDDR
VDDC
VDD
VDDL
VDDA
VDDM
VSSR
VSSC
VSS
VSSL
VSSA
VSSM
P
P
P
P
P
P
P
P
P
P
P
P
46,40,34,28
11, 48
13
19, 25
7
1, 6
31, 37, 43
12, 47
15
20, 26
10
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