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參數(shù)資料
| 型號(hào)： | C9835CY |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems |
| 中文描述： | 低電磁干擾時(shí)鐘發(fā)生器英特爾移動(dòng)133兆赫/ 3的SO - DIMM芯片系統(tǒng) |
| 文件頁(yè)數(shù)： | 9/18頁(yè) |
| 文件大?。?/td> | 343K |
| 代理商： | C9835CY |
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C9835
Document #: 38-07303 Rev. **
Page 9 of 18
Byte 4: VCH Clock Register (1 = Enable, 0 = Disable)
@Pup
[
17
]
Pin#
[
18
]
SMBus Test Circuitry
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for
maximum efficiency in minimizing EMI radiation generated by
repetitive digital signals, mainly clocks. A clock accumulates
EM energy at the center frequency it is generating. Spread
Spectrum distributes this energy over a small frequency
bandwidth therefore distributing an even amount of energy
over a wider spectrum. This technique is achieved by
modulating the clock either down or around the center (see
Figure 7
below) of its resting frequency by a certain
percentage (which also determines the energy distribution
bandwidth). In this device, Spread Spectrum is enabled by
setting SMBUS Byte0,Bit3 = 1. The default of the device at
Notes:
17. The @Pup column gives the default state at power-up
18. The Pin# column lists the relevant pin number where applicable.
power up keeps the Spread Spectrum disabled, it is therefore,
important to have SMBUS accessibility to turn-on the Spread
Spectrum function. Once the Spread Spectrum is enabled, the
spread bandwidth option is selected by SST(0:2) in SMBUS
Byte 5, bits 5, 6, and 7 . See
Table 7
below.
In Down Spread mode the center frequency is shifted down
from its rested (non-spread) value by
of the total spread %
(e.g., assuming the center frequency is 100 MHz in
non-spread mode; when down spread of
–
0.5% is enabled,
the center frequency shifts to 99.75 MHz.). In Center Spread
Mode, the center frequency remains the same as in
non-spread mode.
Bit
Description
7
0
36
VCH_CLK SSC Mode Enable
“
0
”
= 48 MHZ (non-SSCG)
“
1
”
= 66.6 MHz (SSCG applicable when Byte 0,Bit3 = 1)
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
–
–
–
–
–
–
–
Byte 5: SSCG Control Register (1 = Enable, 0 = Disable)
@Pup
[17]
Pin#
[
18
]
7
0
–
6
0
–
5
0
–
4
0
–
3
0
–
2
0
–
1
0
–
0
0
–
Bit
Description
Spread Mode (0 = down, 1 = center)
Selects spread bandwidth. See
Table 5
.
Selects spread bandwidth. See
Table 5
.
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
ESEL1 Expanded Freq. Selection MSB, See
Table 2
.
ESEL0 Expanded Freq. Selection LSB, See
Table 2
.
2.2 K
Device under
SDATA
DATAIN
SCLK
DATAOU
CLOCK
+ 5V
+ 5V
+ 5V
2.2 K
2.2 K
Figure 6. SMBUS Test Circuitry
[19]
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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