參數(shù)資料
型號: C9832HT
英文描述: Up to 5A ULDO linear regulator
中文描述: CPU系統(tǒng)時鐘發(fā)生器|采用TSSOP | 56PIN |塑料
文件頁數(shù): 7/24頁
文件大小: 169K
代理商: C9832HT
C9832H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
5/24/2001
Page 7 of 24
Approved Product
AC Parameters
66 MHz
Min
47.5
69.841
.7Vdd
0
-
133 MHz
Min
47.5
69.841
.7Vdd
0
-
100 MHz
Min
47.5
69.841
.7Vdd
0
-
200 MHz
Min
Symbol
TDC
TPeriod
VHIGH
VLOW
Tr / Tf
Parameter
Xin Duty Cycle
Xin period
Xin High Voltage
Xin Low Voltage
Xin rise and fall
times
Xin Cycle to Cycle
Jitter
Max
52.5
71.0
Vdd
.3Vdd
10.0
Max
52.5
71.0
Vdd
.3Vdd
10.0
Max
52.5
71.0
Vdd
.3Vdd
10.0
Max
Units
%
nS
Volts
Volts
nS
Notes
1, 11, 14
1, 2, 4, 11
13
TCCJ
-
500
-
500
-
500
pS
2, 5, 11
CPU at 0.7Volts Timing
150
TSKEW
Any CPU to CPU
clock Skew
CPU Cycle to
Cycle Jitter
CPU and CPU#
Duty Cycle
CPU and CPU#
period
CPU and CPU#
rise and fall times
-
150
-
-
150
pS
2, 5, 17
TCCJ
-
200
-
200
-
200
200
pS
2, 17, 22
TDC
45
55
45
55
45
55
45
55
%
5, 17, 22
TPeriod
14.8
15.3
7.3
7.65
9.8
10.2
4.8
5.2
nS
5, 17, 22
Tr / Tf
175
600
175
600
175
600
175
600
ps
5, 6, 25
Rise.Fall Matching
Rise Time Variation
Fall Time Variation
crossing point
voltage at 0.7 V
swing
-
-
-
280
20%
150
150
430
-
-
-
20%
150
150
430
20%
150
150
430
-
20%
150
150
430
-
6, 21, 22
6, 22
6, 22
5, 22
DeltaTr
DeltaTf
Vcross
-
-
ps
ps
mV
-
280
280
280
CPU at 1.0 Volts Timing
150
TSKEW
Any CPU to any
CPU clock Skew
CPU Cycle to
Cycle Jitter
CPU and CPU#
Duty Cycle
CPU and CPU#
period
CPU and CPU#
rise and fall times
-
150
-
-
150
pS
2, 5, 17
TCCJ
-
200
-
200
-
200
200
pS
2, 17
TDC
45
55
45
55
45
55
45
55
%
5, 17
TPeriod
14.8
15.3
7.3
7.65
9.8
10.2
4.8
5.2
nS
5, 17
Tr / Tf
300
600
300
600
300
600
300
600
ps
5, 7, 25
Rise.Fall
Matching
Vcross
20%
20%
20%
20%
7, 21, 22
Cross point at 1.0
Volt swing
Rise Time Variation
Fall Time Variation
400
600
400
600
400
600
400
600
mV
DeltaTr
DeltaTf
-
-
150
150
-
-
150
150
-
-
150
150
150
150
ps
ps
7
7
-
TDC
TPeriod
THIGH
TLOW
Tr / Tf
3V66 Duty Cycle
3V66 period
3V66 high time
3V66 low time
3V66 rise and fall
times
3V66 to 3V66 clock
skew
3V66 to 3V66 clock
skew
DRCG Cycle to
Cycle Jitter
45
15.0
4.95
4.55
0.5
55
15.3
-
-
2.0
45
15.0
4.95
4.55
0.5
55
15.3
-
-
2.0
45
15.0
4.95
4.55
0.5
55
15.3
-
-
2.0
45
15.0
4.95
4.55
0.5
55
15.3
-
-
2.0
%
nS
nS
nS
nS
2, 4
1, 2, 4
19
20
3
Tskew
Unbuffered
Tskew
Buffered
TCCJ
-
500
-
500
-
500
-
500
pS
2, 4
-
250
-
250
-
250
-
250
pS
2, 4
-
250
-
250
-
250
-
250
pS
2, 4
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