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參數(shù)資料
| 型號(hào)： | C9827JY |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 21/25頁 |
| 文件大小： | 170K |
| 代理商： | C9827JY |
C9827J
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07107 Rev. **
5/24/2001
Page 21 of 25
VTT_PWRGD# Timing Diagram
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3mS
Delay
State 0
State 2
State 3
Wait for
VTT_GD#
Sample Sels
Off
Off
On
On
State 1
(Note A)
Note A: Device is not effected, VTT_PWRGD# is ignored.
Clock Generator Power Up/Run State Diagram
VTWG#
=Lw
Delay 0.25mS
S1
Power Off
S0
VDDA = 2.0V
Sample
Inputs (pins
54,55)
S2
VDD3.3 = Off
Normal
Operation
S3
Enable Outputs
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