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參數(shù)資料
| 型號(hào)： | C9827H |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | High Performance Pentium 4 Clock Synthesizer |
| 中文描述： | 高性能奔騰4時(shí)鐘合成器 |
| 文件頁(yè)數(shù)： | 13/25頁(yè) |
| 文件大?。?/td> | 171K |
| 代理商： | C9827H |
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C9827H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 13 of 25
Approved Product
Group Timing Relationship and Tolerances
Offset
2.5 nS
0.0 nS
2.5 nS
Tolerance
±
1.0 nS
±
1.0 nS
±
1.0 nS
Conditions
3V66 Leads PCI (un-buffered mode)
0 degrees phase shift
66B leads PCI (buffered mode)
3V66 to PCI
USB to DOT 48M Skew
66B(0:2) to PCI offset
USB and DOT 48M Phase Relationship
The 48MUSB and 48MDOT clocks are in phase. It is understood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for VCH (48MHz) operation it is also in phase with the USB
and DOT outputs.
USB48M
DOT48M
48MUSB and 48MDOT Phase Relationship Figure
66IN to 66B(0:2) Buffered Prop Delay
The 66IN to 66B(0:2) output delay is shown below.
66IN
66CB0:2)
Tpd
66IN to 66B(0:2) Output Delay Figure
The Tpd is the prop delay from the input pin (66IN) to the output pins (66B[0:2]). The outputs’ variation of Tpd is
described in the AC parameters section of this data sheet. The measurement taken at 1.5 volts.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| C9827HT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High Performance Pentium 4 Clock Synthesizer |
| C9827HY | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High Performance Pentium 4 Clock Synthesizer |
| C9827JT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU SYSTEM CLOCK GENERATOR|TSSOP|56PIN|PLASTIC |
| C9827JY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU SYSTEM CLOCK GENERATOR|SSOP|56PIN|PLASTIC |
| C982P | 制造商:PERKINELMER 制造商全稱:PerkinElmer Optoelectronics 功能描述:CHANNEL PHOTO MULTIPLIER |
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