參數(shù)資料
型號(hào): C9811X2AYB
英文描述: Up to 5A ULDO linear regulator
中文描述: CPU系統(tǒng)時(shí)鐘發(fā)生器| SSOP封裝| 56PIN |塑料
文件頁(yè)數(shù): 3/17頁(yè)
文件大?。?/td> 232K
代理商: C9811X2AYB
Low EMI Clock Generator for Intel
810 Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 3 of 17
APPROVED PRODUCT
C9811x2
Test Mode Function
Test Mode Functionality
SEL1
SEL0
0
1
CPU
TCLK
÷
2
SDRAM
TCLK
÷
2
3V66
TCLK
÷
3
PCI
48 MHz
TCLK
÷
2
REF
TCLK
IOAPIC
TCLK
÷
6
TCLK
÷
6
Table 2
Note
:
TCLK is a test clock over driven on the XIN input during test mode.
Power Management Functions
Power Management on this device is controlled by a single pin, PD# (pin32). When PD# is high (default) the device is in
running and all signals are active.
When PD# is asserted (forced) low, the device is in shutdown (or in power down) mode and all power supplies (3.3V and
2.5V except for VDDA/pin 22) may be removed. When in power down, all outputs are synchronously stopped in a low
state (see Fig.2 below), all PLL
s are shut off, and the crystal oscillator is disabled. When the device is shutdown the I
2
C
function is also disabled.
Power Management Timing
PD#
PCI(1:6)
CPU(1:3)
Fig.2
Power Management Current
PD#
,
SEL[1..0]
(CPU Clock)
0XX (Power down)
110 (66MHz)
111 (100MHz)
Maximum 2.5 Volt Current
Consumption (VDD2.5 =2.625)
100 μA
70 mA
100 mA
Table 3
Maximum 3.3 Volt Current Consumption
(VDD3.3 = 3.465 V)
200 μA
280 mA
280 mA
When exiting the power down mode, the designer must supply power to the VDD pins first, a minimum of 200mS before releasing
the PD# pin high.
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