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參數(shù)資料
| 型號(hào)： | C9805CYB |
| 英文描述： | Quad line receivers |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 102K |
| 代理商： | C9805CYB |
C9805
Low EMI Clock Generator for Pentium
II CPU Systems with Power Management
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
http://www.imicorp.com
Rev 1.5
9/2/1999
Page 6 of 10
Spectrum Spread Clocking
Spectrum Analysis
Spectrum Spreading Selection Table
Min (MHz)
Center (MHz)
99.5
99.75
126.4
129.7
Max (MHz)
100
133
CPU Frequency
100
133.3
% OF FREQUENCY SPREADING
0.5% -0.5%% + 0%)
0.5% (-0.5% + 0%)
MODE
Down Spread
Down Spread
Maximum Ratings
Voltage Relative to VSS:
Voltage Relative to VDD:
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
-0.3V
0.3V
-65oC to + 150oC
0oC to +70oC
5V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range: VSS<(Vin
or Vout)<VDD
DC Parameters
Characteristic
Input Low Voltage
Input High Voltage
Input Low Current (@VIL = VSS)
Input High Current (@VIL = VDD)
Tri-State leakage Current
Dynamic Supply Current
Static Supply Current
Symbol
VIL2
VIH2
IIL
IIH
Ioz
Idd3.3V
Isdd
Min
Typ
-
-
Max
0.8
Units
Conditions
-
Vdc
Vdc
μA
μA
μA
mA
mA
SDATA, SCLK
SDATA, SCLK
Pull up
Pull up
2.0
-66
-
-5
5
10
175
2.5
-
-
-
-
-
-
Note 1
PD# Pin at Logic Low
VDD = VDDS = 3.3V
±
5
%, VDDC = 2.5 + 5%, TA = 0oC to +70oC
Note1: CPU frequency = 133 MHz, all outputs loaded to datasheet maximum capacitive loading values and Vdd =
3.465V.
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