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參數(shù)資料
| 型號： | C9805CYB |
| 英文描述： | Quad line receivers |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 102K |
| 代理商： | C9805CYB |
C9805
Low EMI Clock Generator for Pentium
II CPU Systems with Power Management
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
http://www.imicorp.com
Rev 1.5
9/2/1999
Page 5 of 10
Power Management Timing
Latency
Signal
Signal State
No. of rising edges of free
running PCICLK (PCIF)
3 mS
2 mS max.
PD#
1 (normal operation)
0 (power down)
NOTES:
1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable
goes low/high to the first valid clock comes out of the device.
2. Power up latency is when PD# goes inactive (high) to when the first valid clocks are driven from the device.
Power Management Timing
PD#
CPU, PCI, 3V66,
PCI_F, CPU/2, Ref,
IOAPIC
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