參數資料
型號: C8051F300-GMR
廠商: Silicon Laboratories Inc
文件頁數: 66/178頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 11QFN
產品培訓模塊: Serial Communication Overview
標準包裝: 1,500
系列: C8051F30x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),UART/USART
外圍設備: POR,PWM,溫度傳感器,WDT
輸入/輸出數: 8
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數據轉換器: A/D 8x8b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-VFDFN 裸露焊盤
包裝: 帶卷 (TR)
配用: 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
336-1351-ND - KIT REF DES TEMP COMPENS RTC
336-1348-ND - KIT STARTER TOOLSTICK
336-1283-ND - KIT REF DESIGN DTMF DECODER
336-1278-ND - KIT TOOL EVAL SYS IN A USB STICK
336-1246-ND - DEV KIT F300/301/302/303/304/305
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
C8051F300/1/2/3/4/5
158
Rev. 2.9
16.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/
timer and copy it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port
pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused
the capture.
PCA0L
PCA0CPLn
PCA
Timebase
CEXn
Crossbar
Port I/O
PCA0H
Capture
PCA0CPHn
0
1
0
1
(t
o
C
Fn
)
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
F
n
T
O
G
n
P
W
M
n
C
A
P
n
C
A
P
N
n
M
A
T
n
PCA0CN
C
F
C
R
C
F
0
C
F
2
C
F
1
PCA Interrupt
0
000 x
x
Figure 16.4. PCA Capture Mode Diagram
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