參數(shù)資料
型號: C8051F300-GMR
廠商: Silicon Laboratories Inc
文件頁數(shù): 31/178頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 11QFN
產(chǎn)品培訓模塊: Serial Communication Overview
標準包裝: 1,500
系列: C8051F30x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),UART/USART
外圍設備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-VFDFN 裸露焊盤
包裝: 帶卷 (TR)
配用: 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
336-1351-ND - KIT REF DES TEMP COMPENS RTC
336-1348-ND - KIT STARTER TOOLSTICK
336-1283-ND - KIT REF DESIGN DTMF DECODER
336-1278-ND - KIT TOOL EVAL SYS IN A USB STICK
336-1246-ND - DEV KIT F300/301/302/303/304/305
C8051F300/1/2/3/4/5
126
Rev. 2.9
13.5.4. Slave Transmitter Mode
Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH
= 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a
slave address and direction bit (READ in this case) is received. Software responds to the received slave
address with an ACK, or ignores the received slave address with a NACK. If the received address is
ignored, slave interrupts will be inhibited until the next START is detected. If the received slave address is
acknowledged, software should write data to SMB0DAT to force the SMBus into Slave Transmitter Mode.
The switch from Slave Receiver to Slave Transmitter requires software management. Software should per-
form the steps outlined below only when a valid slave address is received (indicated by the label “RX-to-TX
Steps” in Figure 13.8).
Step 1. Set ACK to ‘1’.
Step 2. Write outgoing data to SMB0DAT.
Step 3. Check SMB0DAT.7; if ‘1’, do not perform steps 4, 6 or 7.
Step 4. Set STO to ‘1’.
Step 5. Clear SI to ‘0’.
Step 6. Poll for TXMODE => ‘1’.
Step 7. Clear STO to ‘0’ (must be done before the next ACK cycle).
The interface enters Slave Transmitter Mode and transmits one or more bytes of data (the above steps are
only required before the first byte of the transfer). After each byte is transmitted, the master sends an
acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should be written with the next data byte. If
the acknowledge bit is a NACK, SMB0DAT should not be written to before SI is cleared (Note: an error
condition may be generated if SMB0DAT is written following a received NACK while in Slave Transmitter
Mode). The interface exits Slave Transmitter Mode after receiving a STOP. Note that the interface will
switch to Slave Receiver Mode if SMB0DAT is not written following a Slave Transmitter interrupt.
Figure 13.8 shows a typical Slave Transmitter sequence. Two transmitted data bytes are shown, though
any number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur after the
ACK cycle in this mode.
P
R
SLA
S
Data Byte
A
N
A
S = START
P = STOP
N = NACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupt
Perform RX-to-TX
Steps Here
Figure 13.8. Typical Slave Transmitter Sequence
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